843361ed04
Implement code needed to set up emulation of MCIMX7SABRE board from NXP. For more info about the HW see: https://www.nxp.com/support/developer-resources/hardware-development-tools/sabre-development-system/sabre-board-for-smart-devices-based-on-the-i.mx-7dual-applications-processors:MCIMX7SABRE Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
91 lines
2.7 KiB
C
91 lines
2.7 KiB
C
/*
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* Copyright (c) 2018, Impinj, Inc.
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*
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* MCIMX7D_SABRE Board System emulation.
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This code is licensed under the GPL, version 2 or later.
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* See the file `COPYING' in the top level directory.
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*
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* It (partially) emulates a mcimx7d_sabre board, with a Freescale
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* i.MX7 SoC
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "hw/arm/fsl-imx7.h"
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#include "hw/boards.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/device_tree.h"
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#include "qemu/error-report.h"
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#include "sysemu/qtest.h"
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#include "net/net.h"
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typedef struct {
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FslIMX7State soc;
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MemoryRegion ram;
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} MCIMX7Sabre;
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static void mcimx7d_sabre_init(MachineState *machine)
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{
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static struct arm_boot_info boot_info;
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MCIMX7Sabre *s = g_new0(MCIMX7Sabre, 1);
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Object *soc;
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int i;
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if (machine->ram_size > FSL_IMX7_MMDC_SIZE) {
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error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
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machine->ram_size, FSL_IMX7_MMDC_SIZE);
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exit(1);
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}
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boot_info = (struct arm_boot_info) {
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.loader_start = FSL_IMX7_MMDC_ADDR,
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.board_id = -1,
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.ram_size = machine->ram_size,
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.kernel_filename = machine->kernel_filename,
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.kernel_cmdline = machine->kernel_cmdline,
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.initrd_filename = machine->initrd_filename,
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.nb_cpus = smp_cpus,
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};
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object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7);
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soc = OBJECT(&s->soc);
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object_property_add_child(OBJECT(machine), "soc", soc, &error_fatal);
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object_property_set_bool(soc, true, "realized", &error_fatal);
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memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram",
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machine->ram_size);
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memory_region_add_subregion(get_system_memory(),
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FSL_IMX7_MMDC_ADDR, &s->ram);
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for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
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BusState *bus;
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DeviceState *carddev;
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DriveInfo *di;
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BlockBackend *blk;
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di = drive_get_next(IF_SD);
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blk = di ? blk_by_legacy_dinfo(di) : NULL;
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bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus");
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carddev = qdev_create(bus, TYPE_SD_CARD);
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qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
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object_property_set_bool(OBJECT(carddev), true,
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"realized", &error_fatal);
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}
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if (!qtest_enabled()) {
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arm_load_kernel(&s->soc.cpu[0], &boot_info);
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}
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}
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static void mcimx7d_sabre_machine_init(MachineClass *mc)
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{
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mc->desc = "Freescale i.MX7 DUAL SABRE (Cortex A7)";
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mc->init = mcimx7d_sabre_init;
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mc->max_cpus = FSL_IMX7_NUM_CPUS;
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}
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DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init)
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