Peter Maydell 019076b036 target/arm: Implement VLSTM for v7M CPUs with an FPU ...

Implement the VLSTM instruction for v7M for the FPU present case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-25-peter.maydell@linaro.org

2019-04-29 17:36:03 +01:00

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alpha

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

arm

target/arm: Implement VLSTM for v7M CPUs with an FPU

2019-04-29 17:36:03 +01:00

cris

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

hppa

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

i386

Add tcg_gen_extract2_*.

2019-04-28 11:43:10 +01:00

lm32

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

m68k

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

microblaze

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

mips

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

moxie

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

nios2

Add Nios II semihosting support.

2019-04-29 16:09:51 +01:00

openrisc

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

ppc

Add tcg_gen_extract2_*.

2019-04-28 11:43:10 +01:00

riscv

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

s390x

Add tcg_gen_extract2_*.

2019-04-28 11:43:10 +01:00

sh4

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

sparc

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

tilegx

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

tricore

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

unicore32

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00

xtensa

tcg: Hoist max_insns computation to tb_gen_code

2019-04-24 13:04:33 -07:00