8700ee15de
Previously not all references mentioned any spec version at all. Given r3.1 is the current specification available for evaluation at www.computeexpresslink.org update references to refer to that. Hopefully this won't become a never ending job. A few structure definitions have been updated to add new fields. Defaults of 0 and read only are valid choices for these new DVSEC registers so go with that for now. There are additional error codes and some of the 'questions' in the comments are resolved now. Update documentation reference to point to the CXL r3.1 specification with naming closer to what is on the cover. For cases where there are structure version numbers, add defines so they can be found next to the register definitions. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126121636.24611-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
194 lines
4.8 KiB
C
194 lines
4.8 KiB
C
/*
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* QEMU CXL PCI interfaces
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*
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* Copyright (c) 2020 Intel
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef CXL_PCI_H
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#define CXL_PCI_H
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#define CXL_VENDOR_ID 0x1e98
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#define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */
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#define PCIE_DVSEC_ID_OFFSET 0x8
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#define PCIE_CXL_DEVICE_DVSEC_LENGTH 0x3C
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#define PCIE_CXL31_DEVICE_DVSEC_REVID 3
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#define EXTENSIONS_PORT_DVSEC_LENGTH 0x28
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#define EXTENSIONS_PORT_DVSEC_REVID 0
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#define GPF_PORT_DVSEC_LENGTH 0x10
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#define GPF_PORT_DVSEC_REVID 0
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#define GPF_DEVICE_DVSEC_LENGTH 0x10
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#define GPF_DEVICE_DVSEC_REVID 0
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#define PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH 0x20
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#define PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID 2
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#define REG_LOC_DVSEC_LENGTH 0x24
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#define REG_LOC_DVSEC_REVID 0
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enum {
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PCIE_CXL_DEVICE_DVSEC = 0,
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NON_CXL_FUNCTION_MAP_DVSEC = 2,
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EXTENSIONS_PORT_DVSEC = 3,
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GPF_PORT_DVSEC = 4,
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GPF_DEVICE_DVSEC = 5,
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PCIE_FLEXBUS_PORT_DVSEC = 7,
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REG_LOC_DVSEC = 8,
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MLD_DVSEC = 9,
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CXL20_MAX_DVSEC
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};
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typedef struct DVSECHeader {
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uint32_t cap_hdr;
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uint32_t dv_hdr1;
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uint16_t dv_hdr2;
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} QEMU_PACKED DVSECHeader;
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QEMU_BUILD_BUG_ON(sizeof(DVSECHeader) != 10);
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/*
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* CXL r3.1 Table 8-2: CXL DVSEC ID Assignment
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* Devices must implement certain DVSEC IDs, and can [optionally]
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* implement others.
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* (x) - IDs in Table 8-2.
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*
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* CXL RCD (D1): 0, [2], [5], 7, [8], A - Not emulated yet
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* CXL RCD USP (UP1): 7, [8] - Not emulated yet
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* CXL RCH DSP (DP1): 7, [8]
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* CXL SLD (D2): 0, [2], 5, 7, 8, [A]
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* CXL LD (LD): 0, [2], 5, 7, 8
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* CXL RP (R): 3, 4, 7, 8
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* CXL Switch USP (USP): [2], 7, 8
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* CXL Switch DSP (DSP): 3, 4, 7, 8
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* FM-Owned LD (FMLD): 0, [2], 7, 8, 9
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*/
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/*
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* CXL r3.1 Section 8.1.3: PCIe DVSEC for Devices
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* DVSEC ID: 0, Revision: 3
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*/
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typedef struct CXLDVSECDevice {
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DVSECHeader hdr;
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uint16_t cap;
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uint16_t ctrl;
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uint16_t status;
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uint16_t ctrl2;
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uint16_t status2;
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uint16_t lock;
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uint16_t cap2;
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uint32_t range1_size_hi;
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uint32_t range1_size_lo;
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uint32_t range1_base_hi;
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uint32_t range1_base_lo;
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uint32_t range2_size_hi;
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uint32_t range2_size_lo;
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uint32_t range2_base_hi;
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uint32_t range2_base_lo;
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uint16_t cap3;
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} QEMU_PACKED CXLDVSECDevice;
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QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != 0x3A);
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/*
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* CXL r3.1 Section 8.1.5: CXL Extensions DVSEC for Ports
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* DVSEC ID: 3, Revision: 0
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*/
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typedef struct CXLDVSECPortExt {
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DVSECHeader hdr;
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uint16_t status;
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uint16_t control;
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uint8_t alt_bus_base;
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uint8_t alt_bus_limit;
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uint16_t alt_memory_base;
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uint16_t alt_memory_limit;
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uint16_t alt_prefetch_base;
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uint16_t alt_prefetch_limit;
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uint32_t alt_prefetch_base_high;
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uint32_t alt_prefetch_limit_high;
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uint32_t rcrb_base;
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uint32_t rcrb_base_high;
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} CXLDVSECPortExt;
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QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExt) != 0x28);
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#define PORT_CONTROL_OFFSET 0xc
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#define PORT_CONTROL_UNMASK_SBR 1
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#define PORT_CONTROL_ALT_MEMID_EN 4
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/*
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* CXL r3.1 Section 8.1.6: GPF DVSEC for CXL Port
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* DVSEC ID: 4, Revision: 0
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*/
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typedef struct CXLDVSECPortGPF {
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DVSECHeader hdr;
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uint16_t rsvd;
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uint16_t phase1_ctrl;
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uint16_t phase2_ctrl;
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} CXLDVSECPortGPF;
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QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortGPF) != 0x10);
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/*
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* CXL r3.1 Section 8.1.7: GPF DVSEC for CXL Device
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* DVSEC ID: 5, Revision 0
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*/
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typedef struct CXLDVSECDeviceGPF {
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DVSECHeader hdr;
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uint16_t phase2_duration;
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uint32_t phase2_power;
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} CXLDVSECDeviceGPF;
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QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDeviceGPF) != 0x10);
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/*
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* CXL r3.1 Section 8.1.8: PCIe DVSEC for Flex Bus Port
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* CXL r3.1 Section 8.2.1.3: Flex Bus Port DVSEC
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* DVSEC ID: 7, Revision 2
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*/
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typedef struct CXLDVSECPortFlexBus {
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DVSECHeader hdr;
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uint16_t cap;
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uint16_t ctrl;
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uint16_t status;
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uint32_t rcvd_mod_ts_data_phase1;
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uint32_t cap2;
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uint32_t ctrl2;
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uint32_t status2;
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} CXLDVSECPortFlexBus;
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QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus) != 0x20);
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/*
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* CXL r3.1 Section 8.1.9: Register Locator DVSEC
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* DVSEC ID: 8, Revision 0
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*/
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typedef struct CXLDVSECRegisterLocator {
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DVSECHeader hdr;
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uint16_t rsvd;
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uint32_t reg0_base_lo;
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uint32_t reg0_base_hi;
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uint32_t reg1_base_lo;
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uint32_t reg1_base_hi;
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uint32_t reg2_base_lo;
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uint32_t reg2_base_hi;
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} CXLDVSECRegisterLocator;
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QEMU_BUILD_BUG_ON(sizeof(CXLDVSECRegisterLocator) != 0x24);
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/* BAR Equivalence Indicator */
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#define BEI_BAR_10H 0
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#define BEI_BAR_14H 1
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#define BEI_BAR_18H 2
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#define BEI_BAR_1cH 3
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#define BEI_BAR_20H 4
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#define BEI_BAR_24H 5
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/* Register Block Identifier */
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#define RBI_EMPTY 0
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#define RBI_COMPONENT_REG (1 << 8)
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#define RBI_BAR_VIRT_ACL (2 << 8)
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#define RBI_CXL_DEVICE_REG (3 << 8)
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#endif
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