qemu/target/xtensa
Peter Maydell e32c41e4f6 target/xtensa updates:
- refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting);
 - support icount; run target/xtensa TCG tests with icount;
 - implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYh/EHAAoJEFH5zJH4P6BEpbMP/ilUpDqeSJNP7k1oObABd0cK
 TFOQ3eXtjvmsl9YT17VU8bQpGHZ9R9qP37TcxPBfWAMs/IMtxCCEAclZwEKpGbrB
 L+GypHH2uXvsf4kH2SvElLTULvhOLlxEkfROkxJ++Pverhk/D8JAVxWNb1C4AU/z
 YIIyH8G2Jj2p4ZYvD9OH0Jmv4FfPWljb1unJzu8Y6XynY/Zh7B4xEsvx44E09/l5
 m450tL+Bs/3faoQgznRUMNR3pCUKYBpQEV1pr0Rbcrs/mp58CH71HyAhr0fH/5OT
 yhD7CGj7e6NqhV+vJvnoU6Z5wTRVUD1Reeb8EIzvqLz+4FJTV9L6BWHEIjvZy4TK
 EIakPNl9jbBRxzAwx8PGXm3xxyTznOs/c+K0u2zcFHPnUxnfTmk+MtkfeTjNvx3x
 jiaSXhkaMguf1dOzhiJbjS7s6Kl6NIu7Pta28ItovOOR4AgHbHz6CVHg5Li1bCD9
 dyjwnwflb8dWXQRojg6cA1qQBiq323+2lKz0IaUUtErnbGNst5sRIlAjxN9wjn0H
 giHPspisKV431vN4ZQnEAmOikNfyGd53b/r+a2na0pP1MaYJ0of5Rl0R6YwNfrUa
 MWp0AVF/+qG9ZBpuH8m+1oa3x1Fnc3+2fvWDafcS75lBRa7eyGuHabpO450bOpHB
 ftrtVBYDRt3+HAoAYKHT
 =WOcm
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into staging

target/xtensa updates:

- refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting);
- support icount; run target/xtensa TCG tests with icount;
- implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER.

# gpg: Signature made Wed 25 Jan 2017 00:27:51 GMT
# gpg:                using RSA key 0x51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20170124-xtensa:
  target-xtensa: implement RER/WER instructions
  target/xtensa: tests: clean up interrupt tests
  target/xtensa: tests: add memctl test
  target/xtensa: implement MEMCTL SR
  target/xtensa: fix ICACHE/DCACHE options detection
  target/xtensa: tests: add ccount write tests
  target/xtensa: tests: replace hardcoded interrupt masks
  target/xtensa: tests: fix timer tests
  target/xtensa: tests: run tests with icount
  target/xtensa: don't continue translation after exception
  target/xtensa: support icount
  target/xtensa: refactor CCOUNT/CCOMPARE
  target/xtensa: implement RUNSTALL
  target/xtensa: add static vectors selection

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-25 16:36:57 +00:00
..
core-dc232b Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
core-dc233c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
core-fsf Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
core-dc232b.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
core-dc233c.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
core-fsf.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
cpu-qom.h Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
cpu.c target-xtensa: implement RER/WER instructions 2017-01-16 19:19:03 -08:00
cpu.h target-xtensa: implement RER/WER instructions 2017-01-16 19:19:03 -08:00
gdbstub.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
helper.c target/xtensa: implement RUNSTALL 2017-01-15 13:01:55 -08:00
helper.h target/xtensa updates: 2017-01-25 16:36:57 +00:00
import_core.sh Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
Makefile.objs Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
monitor.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
op_helper.c target/xtensa updates: 2017-01-25 16:36:57 +00:00
overlay_tool.h target-xtensa: implement RER/WER instructions 2017-01-16 19:19:03 -08:00
translate.c target/xtensa updates: 2017-01-25 16:36:57 +00:00
xtensa-semi.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00