qemu/target/i386
Paolo Bonzini c46f68bd7d target/i386: pcrel: store low bits of physical address in data[0]
For PC-relative translation blocks, env->eip changes during the
execution of a translation block, Therefore, QEMU must be able to
recover an instruction's PC just from the TranslationBlock struct and
the instruction data with.  Because a TB will not span two pages, QEMU
stores all the low bits of EIP in the instruction data and replaces them
in x86_restore_state_to_opc.  Bits 12 and higher (which may vary between
executions of a PCREL TB, since these only use the physical address in
the hash key) are kept unmodified from env->eip.  The assumption is that
these bits of EIP, unlike bits 0-11, will not change as the translation
block executes.

Unfortunately, this is incorrect when the CS base is not aligned to a page.
Then the linear address of the instructions (i.e. the one with the
CS base addred) indeed will never span two pages, but bits 12+ of EIP
can actually change.  For example, if CS base is 0x80262200 and EIP =
0x6FF4, the first instruction in the translation block will be at linear
address 0x802691F4.  Even a very small TB will cross to EIP = 0x7xxx,
while the linear addresses will remain comfortably within a single page.

The fix is simply to use the low bits of the linear address for data[0],
since those don't change.  Then x86_restore_state_to_opc uses tb->cs_base
to compute a temporary linear address (referring to some unknown
instruction in the TB, but with the correct values of bits 12 and higher);
the low bits are replaced with data[0], and EIP is obtained by subtracting
again the CS base.

Huge thanks to Mark Cave-Ayland for the image and initial debugging,
and to Gitlab user @kjliew for help with bisecting another occurrence
of (hopefully!) the same bug.

It should be relatively easy to write a testcase that performs MMIO on
an EIP with different bits 12+ than the first instruction of the translation
block; any help is welcome.

Fixes: e3a79e0e87 ("target/i386: Enable TARGET_TB_PCREL", 2022-10-11)
Cc: qemu-stable@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1759
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1964
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2012
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 729ba8e933)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-20 12:24:50 +03:00
..
hvf target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' 2023-11-07 12:13:27 +01:00
kvm i386/sev: Avoid SEV-ES crash due to missing MSR_EFER_LMA bit 2023-12-06 14:34:11 -05:00
nvmm migration: simplify blockers 2023-10-20 08:51:41 +02:00
tcg target/i386: pcrel: store low bits of physical address in data[0] 2024-01-20 12:24:50 +03:00
whpx migration: simplify blockers 2023-10-20 08:51:41 +02:00
arch_dump.c
arch_memory_mapping.c memory: follow Error API guidelines 2023-10-19 23:13:27 +02:00
cpu-dump.c
cpu-internal.h
cpu-param.h target/i386: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
cpu-sysemu.c target/i386/cpu-sysemu: Inline kvm_apic_in_kernel() 2023-09-07 13:32:37 +02:00
cpu.c target/i386/cpu: Improve error message for property "vendor" 2023-11-17 10:07:52 +01:00
cpu.h target/i386: Fix 32-bit wrapping of pc/eip computation 2023-12-12 13:35:08 -08:00
gdbstub.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
helper.c target/i386/helper: Restrict KVM declarations to system emulation 2023-09-07 13:32:37 +02:00
helper.h target/i386: implement SYSCALL/SYSRET in 32-bit emulators 2023-06-26 10:23:56 +02:00
host-cpu.c *: Add missing includes of qemu/error-report.h 2023-03-22 15:06:57 +00:00
host-cpu.h
Kconfig
machine.c i386: spelling fixes 2023-09-20 07:54:34 +03:00
meson.build meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
monitor.c target/i386/monitor: synchronize cpu state for lapic info 2023-11-07 12:13:27 +01:00
ops_sse.h target/i386: implement SHA instructions 2023-10-25 17:35:07 +02:00
sev-sysemu-stub.c
sev.c migration: simplify blockers 2023-10-20 08:51:41 +02:00
sev.h bulk: Do not declare function prototypes using 'extern' keyword 2023-08-31 19:47:43 +02:00
svm.h target/i386: check intercept for XSETBV 2023-10-17 15:20:53 +02:00
trace-events
trace.h
xsave_helper.c