6ffe9b6669
According to RISC-V Debug specification, the optional textra32 and textra64 trigger CSRs can be used to configure additional matching conditions for the triggers. For example, if the textra.MHSELECT field is set to 4 (mcontext), this trigger will only match or fire if the low bits of mcontext/hcontext equal textra.MHVALUE field. This commit adds the aforementioned matching condition as common trigger matching conditions. Currently, the only legal values of textra.MHSELECT are 0 (ignore) and 4 (mcontext). When textra.MHSELECT is 0, we pass the checking. When textra.MHSELECT is 4, we compare textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240826024657.262553-3-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
157 lines
4.5 KiB
C
157 lines
4.5 KiB
C
/*
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* QEMU RISC-V Native Debug Support
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*
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* Copyright (c) 2022 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_DEBUG_H
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#define RISCV_DEBUG_H
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#include "exec/breakpoint.h"
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#define RV_MAX_TRIGGERS 2
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/* register index of tdata CSRs */
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enum {
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TDATA1 = 0,
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TDATA2,
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TDATA3,
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TDATA_NUM
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};
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typedef enum {
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TRIGGER_TYPE_NO_EXIST = 0, /* trigger does not exist */
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TRIGGER_TYPE_AD_MATCH = 2, /* address/data match trigger */
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TRIGGER_TYPE_INST_CNT = 3, /* instruction count trigger */
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TRIGGER_TYPE_INT = 4, /* interrupt trigger */
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TRIGGER_TYPE_EXCP = 5, /* exception trigger */
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TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */
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TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */
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TRIGGER_TYPE_UNAVAIL = 15, /* trigger exists, but unavailable */
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TRIGGER_TYPE_NUM
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} trigger_type_t;
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/* actions */
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typedef enum {
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DBG_ACTION_NONE = -1, /* sentinel value */
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DBG_ACTION_BP = 0,
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DBG_ACTION_DBG_MODE,
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DBG_ACTION_TRACE0,
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DBG_ACTION_TRACE1,
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DBG_ACTION_TRACE2,
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DBG_ACTION_TRACE3,
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DBG_ACTION_EXT_DBG0 = 8,
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DBG_ACTION_EXT_DBG1
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} trigger_action_t;
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/* tdata1 field masks */
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#define RV32_TYPE(t) ((uint32_t)(t) << 28)
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#define RV32_TYPE_MASK (0xf << 28)
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#define RV32_DMODE BIT(27)
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#define RV32_DATA_MASK 0x7ffffff
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#define RV64_TYPE(t) ((uint64_t)(t) << 60)
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#define RV64_TYPE_MASK (0xfULL << 60)
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#define RV64_DMODE BIT_ULL(59)
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#define RV64_DATA_MASK 0x7ffffffffffffff
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/* mcontrol field masks */
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#define TYPE2_LOAD BIT(0)
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#define TYPE2_STORE BIT(1)
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#define TYPE2_EXEC BIT(2)
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#define TYPE2_U BIT(3)
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#define TYPE2_S BIT(4)
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#define TYPE2_M BIT(6)
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#define TYPE2_MATCH (0xf << 7)
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#define TYPE2_CHAIN BIT(11)
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#define TYPE2_ACTION (0xf << 12)
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#define TYPE2_SIZELO (0x3 << 16)
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#define TYPE2_TIMING BIT(18)
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#define TYPE2_SELECT BIT(19)
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#define TYPE2_HIT BIT(20)
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#define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */
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/* mcontrol6 field masks */
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#define TYPE6_LOAD BIT(0)
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#define TYPE6_STORE BIT(1)
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#define TYPE6_EXEC BIT(2)
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#define TYPE6_U BIT(3)
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#define TYPE6_S BIT(4)
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#define TYPE6_M BIT(6)
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#define TYPE6_MATCH (0xf << 7)
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#define TYPE6_CHAIN BIT(11)
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#define TYPE6_ACTION (0xf << 12)
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#define TYPE6_SIZE (0xf << 16)
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#define TYPE6_TIMING BIT(20)
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#define TYPE6_SELECT BIT(21)
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#define TYPE6_HIT BIT(22)
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#define TYPE6_VU BIT(23)
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#define TYPE6_VS BIT(24)
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/* access size */
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enum {
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SIZE_ANY = 0,
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SIZE_1B,
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SIZE_2B,
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SIZE_4B,
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SIZE_6B,
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SIZE_8B,
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SIZE_10B,
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SIZE_12B,
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SIZE_14B,
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SIZE_16B,
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SIZE_NUM = 16
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};
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/* itrigger filed masks */
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#define ITRIGGER_ACTION 0x3f
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#define ITRIGGER_U BIT(6)
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#define ITRIGGER_S BIT(7)
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#define ITRIGGER_PENDING BIT(8)
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#define ITRIGGER_M BIT(9)
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#define ITRIGGER_COUNT (0x3fff << 10)
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#define ITRIGGER_HIT BIT(24)
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#define ITRIGGER_VU BIT(25)
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#define ITRIGGER_VS BIT(26)
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#define MHSELECT_IGNORE 0
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#define MHSELECT_MCONTEXT 4
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bool tdata_available(CPURISCVState *env, int tdata_index);
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target_ulong tselect_csr_read(CPURISCVState *env);
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void tselect_csr_write(CPURISCVState *env, target_ulong val);
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target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
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void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
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target_ulong tinfo_csr_read(CPURISCVState *env);
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void riscv_cpu_debug_excp_handler(CPUState *cs);
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bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
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bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
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void riscv_trigger_realize(CPURISCVState *env);
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void riscv_trigger_reset_hold(CPURISCVState *env);
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bool riscv_itrigger_enabled(CPURISCVState *env);
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void riscv_itrigger_update_priv(CPURISCVState *env);
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#endif /* RISCV_DEBUG_H */
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