1b3b7693b7
Move the ARM and RISCV specific helpers into their own header file. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luc Michel <lmichel@kalray.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/*
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* Target-specific parts of semihosting/arm-compat-semi.c.
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*
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* Copyright (c) 2005, 2007 CodeSourcery.
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* Copyright (c) 2019, 2022 Linaro
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* Copyright © 2020 by Keith Packard <keithp@keithp.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H
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#define TARGET_RISCV_COMMON_SEMI_TARGET_H
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static inline target_ulong common_semi_arg(CPUState *cs, int argno)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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return env->gpr[xA0 + argno];
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}
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static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->gpr[xA0] = ret;
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}
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static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
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{
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return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
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}
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static inline bool is_64bit_semihosting(CPUArchState *env)
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{
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return riscv_cpu_mxl(env) != MXL_RV32;
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}
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static inline target_ulong common_semi_stack_bottom(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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return env->gpr[xSP];
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}
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static inline bool common_semi_has_synccache(CPUArchState *env)
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{
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return true;
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}
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#endif
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