4de4a4705f
This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing with its successors. This commit
is limited to the recording and filtering of taken branches.
The following changes were made:
- Enabled functionality on P10 processors only due to
performance impact seen with P8 and P9 where it is not
disabled for non problem state branches.
- Added a BHRB buffer for storing branch instruction and
target addresses for taken branches
- Renamed gen_update_cfar to gen_update_branch_history and
added a 'target' parameter to hold the branch target
address and 'inst_type' parameter to use for filtering
- Added TCG code to gen_update_branch_history that stores
data to the BHRB and updates the BHRB offset.
- Added BHRB resource initialization and reset functions
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
35 lines
888 B
C
35 lines
888 B
C
/*
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* PMU emulation helpers for TCG IBM POWER chips
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*
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* Copyright IBM Corp. 2021
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef POWER8_PMU_H
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#define POWER8_PMU_H
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#define BHRB_TYPE_NORECORD 0x00
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#define BHRB_TYPE_CALL 0x01
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#define BHRB_TYPE_INDIRECT 0x02
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#define BHRB_TYPE_COND 0x04
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#define BHRB_TYPE_OTHER 0x08
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#define BHRB_TYPE_XL_FORM 0x10
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
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void cpu_ppc_pmu_init(CPUPPCState *env);
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void pmu_mmcr01a_updated(CPUPPCState *env);
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#else
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static inline void cpu_ppc_pmu_init(CPUPPCState *env) { }
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static inline void pmu_mmcr01a_updated(CPUPPCState *env) { }
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#endif
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#endif
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