7bd1900b36
As the CXLState will no long be accessible via MachineState at time of PXB_CXL realization, come back later from the machine specific code to fill in the missing memory region setup. Only at this stage is it possible to check if cxl=on, so that check is moved to this later point. Note that for multiple host bridges, the allocation order of the register spaces is changed. This will be reflected in ACPI CEDT. Stubs are added to handle case of CONFIG_PXB=n for machines that call these functions. The bus walking logic is common to all machines so add a utility function + stub to cxl-host*. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Message-Id: <20220608145440.26106-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
15 lines
399 B
C
15 lines
399 B
C
/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Stubs for calls made from machines to handle the case where CONFIG_PXB
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* is not enabled.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci-bridge/pci_expander_bridge.h"
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#include "hw/cxl/cxl.h"
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void pxb_cxl_hook_up_registers(CXLState *state, PCIBus *bus, Error **errp) {};
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