d4d5212c54
For the CXL PXB there is additional code after pxb_dev_realize_common()
is called. If that realize failed (e.g. due to an out of range numa_node)
we will get a segfault. Return a bool so the caller can check if the
pxb_dev_realize_common() succeeded or not without having to poke around
in the errp.
Fixes: 4f8db8711c
("hw/pxb: Allow creation of a CXL PXB (host bridge)")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20241014121902.2146424-8-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
561 lines
16 KiB
C
561 lines
16 KiB
C
/*
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* PCI Expander Bridge Device Emulation
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*
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* Copyright (C) 2015 Red Hat Inc
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*
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* Authors:
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/qdev-properties.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci-bridge/pci_expander_bridge.h"
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#include "hw/cxl/cxl.h"
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#include "qemu/range.h"
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#include "qemu/error-report.h"
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#include "qemu/module.h"
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#include "sysemu/numa.h"
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#include "hw/boards.h"
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#include "qom/object.h"
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enum BusType { PCI, PCIE, CXL };
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#define TYPE_PXB_BUS "pxb-bus"
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typedef struct PXBBus PXBBus;
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DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS,
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TYPE_PXB_BUS)
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#define TYPE_PXB_PCIE_BUS "pxb-pcie-bus"
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DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS,
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TYPE_PXB_PCIE_BUS)
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DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS,
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TYPE_PXB_CXL_BUS)
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struct PXBBus {
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/*< private >*/
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PCIBus parent_obj;
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/*< public >*/
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char bus_path[8];
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};
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#define TYPE_PXB_PCIE_DEV "pxb-pcie"
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OBJECT_DECLARE_SIMPLE_TYPE(PXBPCIEDev, PXB_PCIE_DEV)
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static GList *pxb_dev_list;
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#define TYPE_PXB_HOST "pxb-host"
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CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb)
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{
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CXLHost *host = PXB_CXL_HOST(hb);
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return &host->cxl_cstate;
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}
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bool cxl_get_hb_passthrough(PCIHostState *hb)
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{
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CXLHost *host = PXB_CXL_HOST(hb);
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return host->passthrough;
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}
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static int pxb_bus_num(PCIBus *bus)
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{
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PXBDev *pxb = PXB_DEV(bus->parent_dev);
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return pxb->bus_nr;
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}
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static uint16_t pxb_bus_numa_node(PCIBus *bus)
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{
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PXBDev *pxb = PXB_DEV(bus->parent_dev);
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return pxb->numa_node;
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}
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static void prop_pxb_uid_get(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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uint32_t uid = pci_bus_num(PCI_BUS(obj));
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visit_type_uint32(v, name, &uid, errp);
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}
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static void pxb_bus_class_init(ObjectClass *class, void *data)
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{
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PCIBusClass *pbc = PCI_BUS_CLASS(class);
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pbc->bus_num = pxb_bus_num;
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pbc->numa_node = pxb_bus_numa_node;
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object_class_property_add(class, "acpi_uid", "uint32",
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prop_pxb_uid_get, NULL, NULL, NULL);
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object_class_property_set_description(class, "acpi_uid",
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"ACPI Unique ID used to distinguish this PCI Host Bridge / ACPI00016");
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}
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static const TypeInfo pxb_bus_info = {
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.name = TYPE_PXB_BUS,
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.parent = TYPE_PCI_BUS,
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.instance_size = sizeof(PXBBus),
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.class_init = pxb_bus_class_init,
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};
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static const TypeInfo pxb_pcie_bus_info = {
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.name = TYPE_PXB_PCIE_BUS,
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.parent = TYPE_PCIE_BUS,
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.instance_size = sizeof(PXBBus),
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.class_init = pxb_bus_class_init,
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};
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static const TypeInfo pxb_cxl_bus_info = {
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.name = TYPE_PXB_CXL_BUS,
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.parent = TYPE_CXL_BUS,
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.instance_size = sizeof(PXBBus),
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.class_init = pxb_bus_class_init,
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};
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static const char *pxb_host_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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PXBBus *bus = pci_bus_is_cxl(rootbus) ?
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PXB_CXL_BUS(rootbus) :
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pci_bus_is_express(rootbus) ? PXB_PCIE_BUS(rootbus) :
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PXB_BUS(rootbus);
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snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus));
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return bus->bus_path;
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}
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static char *pxb_host_ofw_unit_address(const SysBusDevice *dev)
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{
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const PCIHostState *pxb_host;
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const PCIBus *pxb_bus;
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const PXBDev *pxb_dev;
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int position;
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const DeviceState *pxb_dev_base;
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const PCIHostState *main_host;
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const SysBusDevice *main_host_sbd;
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pxb_host = PCI_HOST_BRIDGE(dev);
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pxb_bus = pxb_host->bus;
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pxb_dev = PXB_DEV(pxb_bus->parent_dev);
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position = g_list_index(pxb_dev_list, pxb_dev);
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assert(position >= 0);
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pxb_dev_base = DEVICE(pxb_dev);
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main_host = PCI_HOST_BRIDGE(pxb_dev_base->parent_bus->parent);
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main_host_sbd = SYS_BUS_DEVICE(main_host);
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if (main_host_sbd->num_mmio > 0) {
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return g_strdup_printf(HWADDR_FMT_plx ",%x",
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main_host_sbd->mmio[0].addr, position + 1);
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}
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if (main_host_sbd->num_pio > 0) {
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return g_strdup_printf("i%04x,%x",
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main_host_sbd->pio[0], position + 1);
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}
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return NULL;
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}
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static void pxb_host_class_init(ObjectClass *class, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(class);
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(class);
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
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dc->fw_name = "pci";
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/* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */
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dc->user_creatable = false;
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sbc->explicit_ofw_unit_address = pxb_host_ofw_unit_address;
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hc->root_bus_path = pxb_host_root_bus_path;
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}
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static const TypeInfo pxb_host_info = {
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.name = TYPE_PXB_HOST,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.class_init = pxb_host_class_init,
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};
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static void pxb_cxl_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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CXLHost *cxl = PXB_CXL_HOST(dev);
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CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
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struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
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cxl_component_register_block_init(OBJECT(dev), cxl_cstate,
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TYPE_PXB_CXL_HOST);
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sysbus_init_mmio(sbd, mr);
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}
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/*
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* Host bridge realization has no means of knowning state associated
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* with a particular machine. As such, it is nececssary to delay
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* final setup of the host bridge register space until later in the
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* machine bring up.
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*/
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void pxb_cxl_hook_up_registers(CXLState *cxl_state, PCIBus *bus, Error **errp)
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{
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PXBCXLDev *pxb = PXB_CXL_DEV(pci_bridge_get_device(bus));
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CXLHost *cxl = pxb->cxl_host_bridge;
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CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
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struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
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hwaddr offset;
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offset = memory_region_size(mr) * cxl_state->next_mr_idx;
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if (offset > memory_region_size(&cxl_state->host_mr)) {
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error_setg(errp, "Insufficient space for pxb cxl host register space");
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return;
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}
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memory_region_add_subregion(&cxl_state->host_mr, offset, mr);
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cxl_state->next_mr_idx++;
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}
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static void pxb_cxl_host_class_init(ObjectClass *class, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(class);
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
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hc->root_bus_path = pxb_host_root_bus_path;
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dc->fw_name = "cxl";
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dc->realize = pxb_cxl_realize;
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/* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */
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dc->user_creatable = false;
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}
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/*
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* This is a device to handle the MMIO for a CXL host bridge. It does nothing
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* else.
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*/
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static const TypeInfo cxl_host_info = {
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.name = TYPE_PXB_CXL_HOST,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(CXLHost),
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.class_init = pxb_cxl_host_class_init,
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};
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/*
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* Registers the PXB bus as a child of pci host root bus.
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*/
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static void pxb_register_bus(PCIDevice *dev, PCIBus *pxb_bus, Error **errp)
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{
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PCIBus *bus = pci_get_bus(dev);
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int pxb_bus_num = pci_bus_num(pxb_bus);
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if (bus->parent_dev) {
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error_setg(errp, "PXB devices can be attached only to root bus");
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return;
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}
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QLIST_FOREACH(bus, &bus->child, sibling) {
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if (pci_bus_num(bus) == pxb_bus_num) {
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error_setg(errp, "Bus %d is already in use", pxb_bus_num);
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return;
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}
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}
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QLIST_INSERT_HEAD(&pci_get_bus(dev)->child, pxb_bus, sibling);
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}
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static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin)
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{
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PCIDevice *pxb = pci_get_bus(pci_dev)->parent_dev;
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/*
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* First carry out normal swizzle to handle
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* multiple root ports on a pxb instance.
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*/
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pin = pci_swizzle_map_irq_fn(pci_dev, pin);
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/*
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* The bios does not index the pxb slot number when
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* it computes the IRQ because it resides on bus 0
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* and not on the current bus.
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* However QEMU routes the irq through bus 0 and adds
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* the pxb slot to the IRQ computation of the PXB
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* device.
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*
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* Synchronize between bios and QEMU by canceling
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* pxb's effect.
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*/
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return pin - PCI_SLOT(pxb->devfn);
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}
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static void pxb_cxl_dev_reset(DeviceState *dev)
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{
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CXLHost *cxl = PXB_CXL_DEV(dev)->cxl_host_bridge;
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CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
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PCIHostState *hb = PCI_HOST_BRIDGE(cxl);
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uint32_t *reg_state = cxl_cstate->crb.cache_mem_registers;
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uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask;
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int dsp_count = 0;
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cxl_component_register_init_common(reg_state, write_msk, CXL2_RC);
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/*
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* The CXL specification allows for host bridges with no HDM decoders
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* if they only have a single root port.
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*/
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if (!PXB_CXL_DEV(dev)->hdm_for_passthrough) {
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dsp_count = pcie_count_ds_ports(hb->bus);
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}
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/* Initial reset will have 0 dsp so wait until > 0 */
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if (dsp_count == 1) {
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cxl->passthrough = true;
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/* Set Capability ID in header to NONE */
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_CAPABILITY_HEADER, ID, 0);
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} else {
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT,
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8);
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}
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}
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static gint pxb_compare(gconstpointer a, gconstpointer b)
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{
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const PXBDev *pxb_a = a, *pxb_b = b;
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return pxb_a->bus_nr < pxb_b->bus_nr ? -1 :
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pxb_a->bus_nr > pxb_b->bus_nr ? 1 :
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0;
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}
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static bool pxb_dev_realize_common(PCIDevice *dev, enum BusType type,
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Error **errp)
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{
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PXBDev *pxb = PXB_DEV(dev);
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DeviceState *ds, *bds = NULL;
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PCIBus *bus;
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const char *dev_name = NULL;
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Error *local_err = NULL;
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MachineState *ms = MACHINE(qdev_get_machine());
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if (ms->numa_state == NULL) {
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error_setg(errp, "NUMA is not supported by this machine-type");
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return false;
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}
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if (pxb->numa_node != NUMA_NODE_UNASSIGNED &&
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pxb->numa_node >= ms->numa_state->num_nodes) {
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error_setg(errp, "Illegal numa node %d", pxb->numa_node);
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return false;
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}
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if (dev->qdev.id && *dev->qdev.id) {
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dev_name = dev->qdev.id;
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}
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ds = qdev_new(type == CXL ? TYPE_PXB_CXL_HOST : TYPE_PXB_HOST);
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if (type == PCIE) {
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bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS);
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} else if (type == CXL) {
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bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS);
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bus->flags |= PCI_BUS_CXL;
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PXB_CXL_DEV(dev)->cxl_host_bridge = PXB_CXL_HOST(ds);
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} else {
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bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS);
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bds = qdev_new("pci-bridge");
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bds->id = g_strdup(dev_name);
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qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->bus_nr);
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qdev_prop_set_bit(bds, PCI_BRIDGE_DEV_PROP_SHPC, false);
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}
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bus->parent_dev = dev;
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bus->address_space_mem = pci_get_bus(dev)->address_space_mem;
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bus->address_space_io = pci_get_bus(dev)->address_space_io;
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bus->map_irq = pxb_map_irq_fn;
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PCI_HOST_BRIDGE(ds)->bus = bus;
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PCI_HOST_BRIDGE(ds)->bypass_iommu = pxb->bypass_iommu;
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pxb_register_bus(dev, bus, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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goto err_register_bus;
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}
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sysbus_realize_and_unref(SYS_BUS_DEVICE(ds), &error_fatal);
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if (bds) {
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qdev_realize_and_unref(bds, &bus->qbus, &error_fatal);
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}
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pci_word_test_and_set_mask(dev->config + PCI_STATUS,
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PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
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pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST);
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pxb_dev_list = g_list_insert_sorted(pxb_dev_list, pxb, pxb_compare);
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return true;
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err_register_bus:
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object_unref(OBJECT(bds));
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object_unparent(OBJECT(bus));
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object_unref(OBJECT(ds));
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return false;
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}
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static void pxb_dev_realize(PCIDevice *dev, Error **errp)
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{
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if (pci_bus_is_express(pci_get_bus(dev))) {
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error_setg(errp, "pxb devices cannot reside on a PCIe bus");
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return;
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}
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pxb_dev_realize_common(dev, PCI, errp);
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}
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static void pxb_dev_exitfn(PCIDevice *pci_dev)
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{
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PXBDev *pxb = PXB_DEV(pci_dev);
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pxb_dev_list = g_list_remove(pxb_dev_list, pxb);
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}
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static Property pxb_dev_properties[] = {
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/* Note: 0 is not a legal PXB bus number. */
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DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0),
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DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED),
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DEFINE_PROP_BOOL("bypass_iommu", PXBDev, bypass_iommu, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pxb_dev_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = pxb_dev_realize;
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k->exit = pxb_dev_exitfn;
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k->vendor_id = PCI_VENDOR_ID_REDHAT;
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k->device_id = PCI_DEVICE_ID_REDHAT_PXB;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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dc->desc = "PCI Expander Bridge";
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device_class_set_props(dc, pxb_dev_properties);
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|
dc->hotpluggable = false;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pxb_dev_info = {
|
|
.name = TYPE_PXB_DEV,
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PXBDev),
|
|
.class_init = pxb_dev_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{ },
|
|
},
|
|
};
|
|
|
|
static void pxb_pcie_dev_realize(PCIDevice *dev, Error **errp)
|
|
{
|
|
if (!pci_bus_is_express(pci_get_bus(dev))) {
|
|
error_setg(errp, "pxb-pcie devices cannot reside on a PCI bus");
|
|
return;
|
|
}
|
|
|
|
pxb_dev_realize_common(dev, PCIE, errp);
|
|
}
|
|
|
|
static void pxb_pcie_dev_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->realize = pxb_pcie_dev_realize;
|
|
k->exit = pxb_dev_exitfn;
|
|
k->vendor_id = PCI_VENDOR_ID_REDHAT;
|
|
k->device_id = PCI_DEVICE_ID_REDHAT_PXB_PCIE;
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
|
|
|
dc->desc = "PCI Express Expander Bridge";
|
|
dc->hotpluggable = false;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pxb_pcie_dev_info = {
|
|
.name = TYPE_PXB_PCIE_DEV,
|
|
.parent = TYPE_PXB_DEV,
|
|
.instance_size = sizeof(PXBPCIEDev),
|
|
.class_init = pxb_pcie_dev_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{ },
|
|
},
|
|
};
|
|
|
|
static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
|
|
{
|
|
/* A CXL PXB's parent bus is still PCIe */
|
|
if (!pci_bus_is_express(pci_get_bus(dev))) {
|
|
error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
|
|
return;
|
|
}
|
|
|
|
if (!pxb_dev_realize_common(dev, CXL, errp)) {
|
|
return;
|
|
}
|
|
pxb_cxl_dev_reset(DEVICE(dev));
|
|
}
|
|
|
|
static Property pxb_cxl_dev_properties[] = {
|
|
DEFINE_PROP_BOOL("hdm_for_passthrough", PXBCXLDev, hdm_for_passthrough, false),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->realize = pxb_cxl_dev_realize;
|
|
k->exit = pxb_dev_exitfn;
|
|
/*
|
|
* XXX: These types of bridges don't actually show up in the hierarchy so
|
|
* vendor, device, class, etc. ids are intentionally left out.
|
|
*/
|
|
|
|
dc->desc = "CXL Host Bridge";
|
|
device_class_set_props(dc, pxb_cxl_dev_properties);
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
|
|
/* Host bridges aren't hotpluggable. FIXME: spec reference */
|
|
dc->hotpluggable = false;
|
|
device_class_set_legacy_reset(dc, pxb_cxl_dev_reset);
|
|
}
|
|
|
|
static const TypeInfo pxb_cxl_dev_info = {
|
|
.name = TYPE_PXB_CXL_DEV,
|
|
.parent = TYPE_PXB_PCIE_DEV,
|
|
.instance_size = sizeof(PXBCXLDev),
|
|
.class_init = pxb_cxl_dev_class_init,
|
|
.interfaces =
|
|
(InterfaceInfo[]){
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{},
|
|
},
|
|
};
|
|
|
|
static void pxb_register_types(void)
|
|
{
|
|
type_register_static(&pxb_bus_info);
|
|
type_register_static(&pxb_pcie_bus_info);
|
|
type_register_static(&pxb_cxl_bus_info);
|
|
type_register_static(&pxb_host_info);
|
|
type_register_static(&cxl_host_info);
|
|
type_register_static(&pxb_dev_info);
|
|
type_register_static(&pxb_pcie_dev_info);
|
|
type_register_static(&pxb_cxl_dev_info);
|
|
}
|
|
|
|
type_init(pxb_register_types)
|