e4ea952fb0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-41-richard.henderson@linaro.org>
225 lines
7.4 KiB
C
225 lines
7.4 KiB
C
/*
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* Allwinner A10 Clock Control Module emulation
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*
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* Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
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*
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* This file is derived from Allwinner H3 CCU,
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* by Niek Linnenbank.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/misc/allwinner-a10-ccm.h"
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/* CCM register offsets */
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enum {
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REG_PLL1_CFG = 0x0000, /* PLL1 Control */
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REG_PLL1_TUN = 0x0004, /* PLL1 Tuning */
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REG_PLL2_CFG = 0x0008, /* PLL2 Control */
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REG_PLL2_TUN = 0x000C, /* PLL2 Tuning */
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REG_PLL3_CFG = 0x0010, /* PLL3 Control */
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REG_PLL4_CFG = 0x0018, /* PLL4 Control */
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REG_PLL5_CFG = 0x0020, /* PLL5 Control */
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REG_PLL5_TUN = 0x0024, /* PLL5 Tuning */
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REG_PLL6_CFG = 0x0028, /* PLL6 Control */
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REG_PLL6_TUN = 0x002C, /* PLL6 Tuning */
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REG_PLL7_CFG = 0x0030, /* PLL7 Control */
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REG_PLL1_TUN2 = 0x0038, /* PLL1 Tuning2 */
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REG_PLL5_TUN2 = 0x003C, /* PLL5 Tuning2 */
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REG_PLL8_CFG = 0x0040, /* PLL8 Control */
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REG_OSC24M_CFG = 0x0050, /* OSC24M Control */
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REG_CPU_AHB_APB0_CFG = 0x0054, /* CPU, AHB and APB0 Divide Ratio */
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};
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#define REG_INDEX(offset) (offset / sizeof(uint32_t))
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/* CCM register reset values */
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enum {
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REG_PLL1_CFG_RST = 0x21005000,
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REG_PLL1_TUN_RST = 0x0A101000,
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REG_PLL2_CFG_RST = 0x08100010,
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REG_PLL2_TUN_RST = 0x00000000,
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REG_PLL3_CFG_RST = 0x0010D063,
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REG_PLL4_CFG_RST = 0x21009911,
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REG_PLL5_CFG_RST = 0x11049280,
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REG_PLL5_TUN_RST = 0x14888000,
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REG_PLL6_CFG_RST = 0x21009911,
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REG_PLL6_TUN_RST = 0x00000000,
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REG_PLL7_CFG_RST = 0x0010D063,
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REG_PLL1_TUN2_RST = 0x00000000,
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REG_PLL5_TUN2_RST = 0x00000000,
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REG_PLL8_CFG_RST = 0x21009911,
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REG_OSC24M_CFG_RST = 0x00138013,
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REG_CPU_AHB_APB0_CFG_RST = 0x00010010,
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};
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static uint64_t allwinner_a10_ccm_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwA10ClockCtlState *s = AW_A10_CCM(opaque);
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const uint32_t idx = REG_INDEX(offset);
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switch (offset) {
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case REG_PLL1_CFG:
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case REG_PLL1_TUN:
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case REG_PLL2_CFG:
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case REG_PLL2_TUN:
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case REG_PLL3_CFG:
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case REG_PLL4_CFG:
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case REG_PLL5_CFG:
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case REG_PLL5_TUN:
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case REG_PLL6_CFG:
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case REG_PLL6_TUN:
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case REG_PLL7_CFG:
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case REG_PLL1_TUN2:
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case REG_PLL5_TUN2:
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case REG_PLL8_CFG:
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case REG_OSC24M_CFG:
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case REG_CPU_AHB_APB0_CFG:
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break;
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case 0x158 ... AW_A10_CCM_IOSIZE:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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return s->regs[idx];
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}
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static void allwinner_a10_ccm_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwA10ClockCtlState *s = AW_A10_CCM(opaque);
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const uint32_t idx = REG_INDEX(offset);
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switch (offset) {
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case REG_PLL1_CFG:
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case REG_PLL1_TUN:
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case REG_PLL2_CFG:
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case REG_PLL2_TUN:
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case REG_PLL3_CFG:
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case REG_PLL4_CFG:
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case REG_PLL5_CFG:
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case REG_PLL5_TUN:
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case REG_PLL6_CFG:
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case REG_PLL6_TUN:
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case REG_PLL7_CFG:
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case REG_PLL1_TUN2:
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case REG_PLL5_TUN2:
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case REG_PLL8_CFG:
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case REG_OSC24M_CFG:
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case REG_CPU_AHB_APB0_CFG:
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break;
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case 0x158 ... AW_A10_CCM_IOSIZE:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
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__func__, (uint32_t)offset);
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break;
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}
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s->regs[idx] = (uint32_t) val;
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}
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static const MemoryRegionOps allwinner_a10_ccm_ops = {
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.read = allwinner_a10_ccm_read,
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.write = allwinner_a10_ccm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static void allwinner_a10_ccm_reset_enter(Object *obj, ResetType type)
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{
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AwA10ClockCtlState *s = AW_A10_CCM(obj);
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/* Set default values for registers */
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s->regs[REG_INDEX(REG_PLL1_CFG)] = REG_PLL1_CFG_RST;
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s->regs[REG_INDEX(REG_PLL1_TUN)] = REG_PLL1_TUN_RST;
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s->regs[REG_INDEX(REG_PLL2_CFG)] = REG_PLL2_CFG_RST;
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s->regs[REG_INDEX(REG_PLL2_TUN)] = REG_PLL2_TUN_RST;
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s->regs[REG_INDEX(REG_PLL3_CFG)] = REG_PLL3_CFG_RST;
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s->regs[REG_INDEX(REG_PLL4_CFG)] = REG_PLL4_CFG_RST;
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s->regs[REG_INDEX(REG_PLL5_CFG)] = REG_PLL5_CFG_RST;
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s->regs[REG_INDEX(REG_PLL5_TUN)] = REG_PLL5_TUN_RST;
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s->regs[REG_INDEX(REG_PLL6_CFG)] = REG_PLL6_CFG_RST;
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s->regs[REG_INDEX(REG_PLL6_TUN)] = REG_PLL6_TUN_RST;
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s->regs[REG_INDEX(REG_PLL7_CFG)] = REG_PLL7_CFG_RST;
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s->regs[REG_INDEX(REG_PLL1_TUN2)] = REG_PLL1_TUN2_RST;
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s->regs[REG_INDEX(REG_PLL5_TUN2)] = REG_PLL5_TUN2_RST;
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s->regs[REG_INDEX(REG_PLL8_CFG)] = REG_PLL8_CFG_RST;
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s->regs[REG_INDEX(REG_OSC24M_CFG)] = REG_OSC24M_CFG_RST;
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s->regs[REG_INDEX(REG_CPU_AHB_APB0_CFG)] = REG_CPU_AHB_APB0_CFG_RST;
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}
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static void allwinner_a10_ccm_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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AwA10ClockCtlState *s = AW_A10_CCM(obj);
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/* Memory mapping */
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memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_ccm_ops, s,
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TYPE_AW_A10_CCM, AW_A10_CCM_IOSIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription allwinner_a10_ccm_vmstate = {
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.name = "allwinner-a10-ccm",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AwA10ClockCtlState, AW_A10_CCM_REGS_NUM),
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VMSTATE_END_OF_LIST()
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}
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};
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static void allwinner_a10_ccm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.enter = allwinner_a10_ccm_reset_enter;
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dc->vmsd = &allwinner_a10_ccm_vmstate;
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}
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static const TypeInfo allwinner_a10_ccm_info = {
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.name = TYPE_AW_A10_CCM,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = allwinner_a10_ccm_init,
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.instance_size = sizeof(AwA10ClockCtlState),
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.class_init = allwinner_a10_ccm_class_init,
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};
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static void allwinner_a10_ccm_register(void)
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{
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type_register_static(&allwinner_a10_ccm_info);
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}
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type_init(allwinner_a10_ccm_register)
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