674b0a5784
hw/pci/pci_bridge.h and hw/cxl/cxl.h include each other. Fortunately, breaking the loop is merely a matter of deleting unnecessary includes from headers, and adding them back in places where they are now missing. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-2-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
93 lines
2.0 KiB
C
93 lines
2.0 KiB
C
/*
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* QEMU Alpha PCI support functions.
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*
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* Some of this isn't very Alpha specific at all.
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*
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* ??? Sparse memory access not implemented.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci_host.h"
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#include "alpha_sys.h"
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#include "qemu/log.h"
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#include "trace.h"
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/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */
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static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
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{
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return 0;
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}
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static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
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{
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}
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const MemoryRegionOps alpha_pci_ignore_ops = {
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.read = ignore_read,
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.write = ignore_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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/* PCI config space reads/writes, to byte-word addressable memory. */
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static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PCIBus *b = opaque;
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return pci_data_read(b, addr, size);
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}
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static void bw_conf1_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIBus *b = opaque;
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pci_data_write(b, addr, val, size);
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}
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const MemoryRegionOps alpha_pci_conf1_ops = {
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.read = bw_conf1_read,
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.write = bw_conf1_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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/* PCI/EISA Interrupt Acknowledge Cycle. */
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static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
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{
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return pic_read_irq(isa_pic);
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}
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static void special_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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trace_alpha_pci_iack_write();
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}
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const MemoryRegionOps alpha_pci_iack_ops = {
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.read = iack_read,
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.write = special_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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