c0d691ab84
The routines in disas-common.c are also used from disas-mon.c. Otherwise the rest of disassembly is only used from tcg. While we're at it, put host and target code into separate files. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
130 lines
3.6 KiB
C
130 lines
3.6 KiB
C
/*
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* Routines for host instruction disassembly.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "disas/disas.h"
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#include "disas/capstone.h"
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#include "disas-internal.h"
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/*
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* Get LENGTH bytes from info's buffer, at host address memaddr.
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* Transfer them to myaddr.
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*/
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static int host_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
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struct disassemble_info *info)
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{
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if (memaddr < info->buffer_vma
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|| memaddr + length > info->buffer_vma + info->buffer_length) {
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/* Out of bounds. Use EIO because GDB uses it. */
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return EIO;
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}
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memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
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return 0;
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}
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/* Print address in hex, truncated to the width of a host virtual address. */
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static void host_print_address(bfd_vma addr, struct disassemble_info *info)
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{
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info->fprintf_func(info->stream, "0x%" PRIxPTR, (uintptr_t)addr);
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}
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static void initialize_debug_host(CPUDebug *s)
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{
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disas_initialize_debug(s);
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s->info.read_memory_func = host_read_memory;
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s->info.print_address_func = host_print_address;
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#if HOST_BIG_ENDIAN
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s->info.endian = BFD_ENDIAN_BIG;
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#else
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s->info.endian = BFD_ENDIAN_LITTLE;
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#endif
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#if defined(CONFIG_TCG_INTERPRETER)
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s->info.print_insn = print_insn_tci;
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#elif defined(__i386__)
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s->info.mach = bfd_mach_i386_i386;
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s->info.cap_arch = CS_ARCH_X86;
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s->info.cap_mode = CS_MODE_32;
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s->info.cap_insn_unit = 1;
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s->info.cap_insn_split = 8;
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#elif defined(__x86_64__)
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s->info.mach = bfd_mach_x86_64;
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s->info.cap_arch = CS_ARCH_X86;
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s->info.cap_mode = CS_MODE_64;
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s->info.cap_insn_unit = 1;
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s->info.cap_insn_split = 8;
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#elif defined(_ARCH_PPC)
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s->info.cap_arch = CS_ARCH_PPC;
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# ifdef _ARCH_PPC64
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s->info.cap_mode = CS_MODE_64;
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# endif
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#elif defined(__riscv)
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#if defined(_ILP32) || (__riscv_xlen == 32)
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s->info.print_insn = print_insn_riscv32;
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#elif defined(_LP64)
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s->info.print_insn = print_insn_riscv64;
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#else
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#error unsupported RISC-V ABI
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#endif
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#elif defined(__aarch64__)
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s->info.cap_arch = CS_ARCH_ARM64;
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#elif defined(__alpha__)
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s->info.print_insn = print_insn_alpha;
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#elif defined(__sparc__)
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s->info.print_insn = print_insn_sparc;
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s->info.mach = bfd_mach_sparc_v9b;
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#elif defined(__arm__)
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/* TCG only generates code for arm mode. */
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s->info.cap_arch = CS_ARCH_ARM;
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#elif defined(__MIPSEB__)
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s->info.print_insn = print_insn_big_mips;
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#elif defined(__MIPSEL__)
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s->info.print_insn = print_insn_little_mips;
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#elif defined(__m68k__)
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s->info.print_insn = print_insn_m68k;
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#elif defined(__s390__)
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s->info.cap_arch = CS_ARCH_SYSZ;
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s->info.cap_insn_unit = 2;
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s->info.cap_insn_split = 6;
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#elif defined(__hppa__)
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s->info.print_insn = print_insn_hppa;
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#elif defined(__loongarch__)
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s->info.print_insn = print_insn_loongarch;
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#endif
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}
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/* Disassemble this for me please... (debugging). */
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void disas(FILE *out, const void *code, size_t size)
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{
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uintptr_t pc;
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int count;
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CPUDebug s;
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initialize_debug_host(&s);
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s.info.fprintf_func = fprintf;
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s.info.stream = out;
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s.info.buffer = code;
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s.info.buffer_vma = (uintptr_t)code;
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s.info.buffer_length = size;
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s.info.show_opcodes = true;
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if (s.info.cap_arch >= 0 && cap_disas_host(&s.info, code, size)) {
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return;
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}
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if (s.info.print_insn == NULL) {
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s.info.print_insn = print_insn_od_host;
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}
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for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
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fprintf(out, "0x%08" PRIxPTR ": ", pc);
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count = s.info.print_insn(pc, &s.info);
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fprintf(out, "\n");
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if (count < 0) {
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break;
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}
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}
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}
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