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65 Commits

Author SHA1 Message Date
Max Filippov
40643d7c0f target-xtensa: implement exceptions 
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov
f0a548b93d target-xtensa: add PS register and access control 
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov
8ffc2d0d97 target-xtensa: implement CACHE group 
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov
28067b2288 target-xtensa: implement SYNC group 
All operations in this group are no-ops, because there are no delayed
side effects.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov
91a5bb76d4 target-xtensa: mark reserved and TBD opcodes 
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov
809377aa52 target-xtensa: implement LSAI group 
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov
3580ecad0a target-xtensa: implement shifts (ST1 and RST1 groups) 
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov
b8132eff89 target-xtensa: implement RST3 group 
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov
2af3da9183 target-xtensa: add special and user registers 
Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.

User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details.

Only registers mapped in sregnames or uregnames are considered valid.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:37 +00:00
Max Filippov
5da4a6a8c5 target-xtensa: implement JX/RET0/CALLX 
Group SNM0 (indirect jumps and calls).

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:37 +00:00
Max Filippov
bd57fb91ae target-xtensa: implement conditional jumps 
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:37 +00:00
Max Filippov
f331fe5e5f target-xtensa: implement RT0 group 
NEG and ABS are the only members of RT0 group.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:36 +00:00
Max Filippov
67882fd177 target-xtensa: implement narrow instructions 
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:36 +00:00
Max Filippov
dedc5eae23 target-xtensa: implement disas_xtensa_insn 
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.

Implement code generation loop with single step/breakpoint checking.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:36 +00:00
Max Filippov
2328826b1d target-xtensa: add target stubs 
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:36 +00:00