use range helper function in msix_write_config().
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Function mask is a mandatory feature in MSIX
spec so not implementing it is a spec violation.
Implement.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
rename ENABLE_OFFSET -> CONTROL_OFFSET, since
same byte includes function mask.
This is in preparation for function mask support.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
PCI spec states:
if a masked vector has its Pending bit set, and the associated
underlying interrupt events are somehow satisfied (usually by software
though the exact manner is function-specific), the function must clear
the Pending bit, to avoid sending a spurious interrupt message later
when software unmasks the vector.
In our case this happens if vector becomes unused.
Clear pending bit in this case.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
On reset, we currently clear all bits in msix control register *except*
enable bit. This is wrong: the spec says we should clear writeable
bits: function mask and enable bit.
Correct this.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This patch is preliminary for 64 bit BAR support.
Introduce dedicated type, pcibus_t, to represent pci bus address/size
instead of uint32_t.
Later this type will be changed to uint64_t.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Fixes a couple of issues with msix table access:
- With misbehaving guests, misaligned 4 byte access could overflow
msix table and cause qemu to segfault. Since PCI spec requires
host to only issue dword-aligned accesses, as a fix,
it's enough to mask the address low bits.
- Tables use pci format, not native format, and so
we must use pci_[sg]et_long on read/write.
Reported-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Since cpu_register_phys_memory does not require size to be a multiple of
target page size, simply make msix page size 0x1000. Do this in msix,
reverting part of 5e520a7d50, as we no
longer have to pass target page around.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b72.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
I don't think it's critical to do this, but it's
best to keep uninit and error recovery consistent.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
MSIX present bit is tested incorrectly, and only happens to work because
the bit we are testing is 0x1. Add braces to fix this.
Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Clean up msix vector usage state on load. Since guest might have control
over it through the device, the device will have to load this state from
file.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This fixes segfault reported by Kevin Wolf,
and simplifies the code in msix_save.
Reported-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Add functions implementing MSI-X support. First user will be virtio-pci.
Note that platform must set a flag to declare MSI supported: this
is a safety measure to avoid breaking platforms which should support
MSI-X but currently lack this in the interrupt controller emulation.
For PC this will be set by APIC.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
