this adds a basic vmdk corruption check. it should detect severe
table corruptions and file truncation.
Signed-off-by: Peter Lieven <pl@kamp.de>
Reviewed-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
The QCOW2 .bdrv_make_empty implementation always returns 0 for success,
but does not actually do anything.
The proper way to not support an optional driver function stub is to
just not implement it, so let's remove the stub.
Signed-off-by: Jeff Cody <jcody@redhat.com>
Reviewed-by: Benoit Canet <benoit@irqsave.net>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
The QED .bdrv_make_empty() implementation does nothing but return
-ENOTSUP, which causes problems in bdrv_commit(). Since the function
stub exists for QED, it is called, which then always returns an error.
The proper way to not support an optional driver function stub is to
just not implement it, so let's remove the stub.
Signed-off-by: Jeff Cody <jcody@redhat.com>
Reviewed-by: Benoit Canet <benoit@irqsave.net>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
The qemu-img.texi / qemu-doc.texi files currently describe the
qcow2/qcow2 encryption thus
"Encryption uses the AES format which is very secure (128 bit
keys). Use a long password (16 characters) to get maximum
protection."
While AES is indeed a strong encryption system, the way that
QCow/QCow2 use it results in a poor/weak encryption system.
Due to the use of predictable IVs, based on the sector number
extended to 128 bits, it is vulnerable to chosen plaintext
attacks which can reveal the existence of encrypted data.
The direct use of the user passphrase as the encryption key
also leads to an inability to change the passphrase of an
image. If passphrase is ever compromised the image data will
all be vulnerable, since it cannot be re-encrypted. The admin
has to clone the image files with a new passphrase and then
use a program like shred to secure erase all the old files.
Recommend against any use of QCow/QCow2 encryption, directing
users to dm-crypt / LUKS which can meet modern cryptography
best practices.
[Changed "Qcow" to "qcow" for consistency.
--Stefan]
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Fix two bugs that would allow changing the state of SGIs through the
ICPENDR and ISPENDRs.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Instead of hardcoding 16 various places in the code, use a define to
make it more clear what is going on.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This implements a subset of the AdvSIMD shift operations (namely all the
none saturating or narrowing ones). The actual shift generation code
itself is common for both the scalar and vector cases but wrapped with
either vector element iteration or the fp reg access.
The rounding operations need to take special care to correctly reflect
the result of adding rounding bits on high bits as the intermediates do
not truncate.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Implement a simple subset of the SIMD 3-same floating point
operations. This includes a common helper function used for both
scalar and vector ops; FABD is the only currently implemented
shared op.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add some of the integer operations in the SIMD 3-same group:
specifically, the comparisons, addition and subtraction.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,
BIT and BIF) from the SIMD 3 register same group (C3.6.16).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add top level decode for the A64 SIMD three regs same group
(C3.6.16), splitting it into the pairwise, logical, float and
integer subgroups.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement the add, sub and compare ops from the SIMD "scalar three same"
group.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement the absolute-difference instructions in the SIMD
three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
SABDL2, UABDL, UABDL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add support for the multiply-accumulate instructions from the
SIMD three-different instructions group (C3.6.15):
* skeleton decode of unallocated encodings and split of
the group into its three sub-parts
* framework for handling the 64x64->128 widening subpart
* implementation of the multiply-accumulate instructions
SMLAL, SMLAL2, UMLAL, UMLAL2, SMLSL, SMLSL2, UMLSL, UMLSL2,
UMULL, UMULL2, SMULL, SMULL2
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP
and VCVTM instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP
and VCVTM instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
VRINTM and VRINTZ instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add support for the AArch32 floating-point VRINTX instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add support for the AArch32 floating-point VRINTZ instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add support for the AArch32 floating-point VRINTR instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This function will be needed for AArch32 ARMv8 support, so move it to
helper.c where it can be used by both targets. Also moves the code out
of line, but as it is quite a large function I don't believe this
should be a significant performance impact.
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
For blizzard, pl110 and tc6393xb this is harmless, but for pxa2xx
Coverity noticed that it is used inside an "if" statement.
Fix it because it's the file with the highest number of defects
in the whole QEMU tree! Use "do...while (0)", or just remove the
semicolon if there's a single statement in the macro.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This patch uses the fact that the midr variable is now a property
This patch sets the midr variable to the boards custom midr
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Convert the MIDR register to a property. This allows boards to later set
a custom MIDR value. This has been done in such a way to maintain
compatibility with all existing CPUs and boards
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 878613f2f12d4162f12629522fd99de8df904856.1390176489.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The code which decides whether to set up the ATAGS data structure on
reset was using the wrong conditional, which meant we were creating
an ATAGS structure when doing a device-tree boot if the dtb was
autogenerated by the board. This is harmless, but unnecessary, so
bring it in to line with user-provided-dtb boots.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1388326833-656-1-git-send-email-peter.maydell@linaro.org
Add support for the SIMD scalar copy instruction group (C3.6.7),
which consists of the single instruction DUP (element, scalar).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This patch adds support for the AdvSIMD modified immediate group
(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf <agraf@suse.de>
[AJB: new decode struct, minor bug fixes, optimisation]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This adds support for the all the AdvSIMD vector copy operations
(ARM ARM 3.6.5).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add support for the SIMD "across lanes" instruction group (C3.6.4).
Signed-off-by: Michael Matz <matz@suse.de>
[PMM: Updated to current codebase, added fp min/max ops,
added unallocated encoding checks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add support for the SIMD ZIP/UZIP/TRN instruction group
(C3.6.3).
Signed-off-by: Michael Matz <matz@suse.de>
[PMM: use new do_vec_get/set etc functions and generally update to new
codebase standards; refactor to pull per-element loop outside switch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add support for the SIMD TBL/TBLX instructions (group C3.6.2).
Signed-off-by: Michael Matz <matz@suse.de>
[PMM: rewritten to do more of the decode in translate-a64.c,
and to do only one 64 bit pass at a time in the helper]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add support for the SIMD EXT instruction (the only one in its
group, C3.6.1).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add decode skeleton and function placeholders for all the SIMD data
processing instructions. Due to the complexity of this part of the
table the normal extract and switch approach gets very messy very
quickly, so we use a simple data-driven pattern-and-mask approach.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement the SIMD ld/st single structure instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This adds support support for the SIMD load/store
multiple category of instructions.
This also brings in a couple of helper functions for manipulating
sections of the SIMD registers:
* do_vec_get - fetch value from a slice of a vector register
* do_vec_set - set a slice of a vector register
which use vec_reg_offset for consistent processing of offsets in an
endian aware manner. There are also additional helpers:
* do_vec_ld - load value into SIMD
* do_vec_st - store value from SIMD
which load or store a slice of a vector register to memory.
These don't zero extend like the fp variants.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJS5nJdAAoJEJykq7OBq3PIUV8H/1Vz4Ug/iI0TgUkbyRtoZ/E3
3C5BCO0SyPnZ91iCzbNXo8IcTYejSPeMT951XSxrz/lg5HDqN+vyA1IQzJUc1Sbn
tP+VYffsRAJ/5jW2Jj2cdCxlAIob60THS8Z3Z/NqubcxTlBcbmuFykZLbLhU+DbU
dow3E+hla/I1A/6bjcQ/8u5a4asp9zqRuvOqwcf7i1kNChfYv2/rCrtiWjQhKktq
uqFX2vVL8lmJanp+lOsZcUID4w0Ot6uJNrtzofxvg7OtMfVPb0G8PMcq8/Zxnz72
NJfKuBsAV7/hwWm5EKKRGJRHko29ymOFkuGQR7e0aF8ZdPA0ByQWnPXmgE1p5V0=
=QnyD
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into staging
Tracing pull request
# gpg: Signature made Mon 27 Jan 2014 14:51:09 GMT using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* stefanha/tags/tracing-pull-request:
trace: fix simple trace "disable" keyword
trace: add glib 2.32+ static GMutex support
trace: [simple] Do not include "trace/simple.h" in generated tracer headers
tracing: start trace processing thread in final child process
Message-id: 1390834386-23139-1-git-send-email-stefanha@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The partial register handling (introduced with commits
420840e58b and
3474b67948 ) aimed to improve intercept
handling performance.
It made the code more complicated though. During development for life
migration/init/reset etc it turned out that this might cause several
hard to debug programming errors. With the introduction of ioeventfd
(and future irqfd patches) the qemu intercept handlers are no longer
hot-path. And therefore the partial register handling can be
removed to simplify the code.
Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com>
CC: Jason J. Herne <jjherne@us.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Acked-by: Alexander Graf <agraf@suse.de>
This includes new unit-tests for acpi by Marcel,
hotplug for pci bridges by myself (piix only so far)
and cpu hotplug for q35.
And a bunch of fixes all over the place as usual.
I included the patch to fix memory alignment for q35
as well - even though it limits 32 bit guests to 3G (they
previously could address more memory with PAE).
To remove the limit, this will have to be fixed in seabios.
I also added self as virtio co-maintainer so I don't need
to troll the list for patches to review.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJS5O2JAAoJECgfDbjSjVRpBRsH/iueYMYqtlIOCFSBf4TSU5LN
3369DwM0EncrEIZhv6jjtX+CSKUca9IXkKcvBBHJOTwhUodGNZ1wJ/FpO9+AhjpB
5XlIcF4nOi2eYDGs/8JToecK+edggTrSjJ8Bg5n7/bEtJ/oNyjTQ0RMX+2jXq1y3
jnpVjO1ntQXkZQZWNM3O+8biVT1o8wJlFhFbYpx4TKgFplPnRrg1gZR3MtnhsZ+M
OoBenpJYrh5Gw52d6HPauMDAux51MjGymzrk2Wmd/w3hPMP9BcxX7NvoapKlGTg9
DkVr7cvbIzZ2JnsRLFNeWsJIupOjl6MwqhGJo5WcB5VS7NZTbVHmtBRvqKa76EU=
=y3wE
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
acpi,pci,pc,virtio fixes and enhancements
This includes new unit-tests for acpi by Marcel,
hotplug for pci bridges by myself (piix only so far)
and cpu hotplug for q35.
And a bunch of fixes all over the place as usual.
I included the patch to fix memory alignment for q35
as well - even though it limits 32 bit guests to 3G (they
previously could address more memory with PAE).
To remove the limit, this will have to be fixed in seabios.
I also added self as virtio co-maintainer so I don't need
to troll the list for patches to review.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Sun 26 Jan 2014 11:12:09 GMT using RSA key ID D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* mst/tags/for_anthony: (35 commits)
MAINTAINERS: add self as virtio co-maintainer
q35: document gigabyte_align
q35: gigabyte alignment for ram
acpi: Fix PCI hole handling on build_srat()
pc: Save size of RAM below 4GB
hw/pci: fix error flow in pci multifunction init
acpi-test: update expected AML since recent changes
pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated
pc: ACPI: unify source of CPU hotplug IO base/len
pc: ACPI: expose PRST IO range via _CRS
pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources
pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources
pc: set PRST base in DSDT depending on chipset
acpi: ich9: add CPU hotplug handling to Q35 machine
acpi: factor out common cpu hotplug code for PIIX4/Q35
acpi-build: enable hotplug for PCI bridges
piix4: add acpi pci hotplug support
pcihp: generalization of piix4 acpi
pci: add pci_for_each_bus_depth_first
pc: make: fix dependencies: rebuild when included file is changed
...
Message-id: 1390735289-15563-1-git-send-email-mst@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJS5nEPAAoJEJykq7OBq3PI2XkH/1+f2mTJydxsg71571fOV+05
IQl5dp14FZe+b3R4gRIEkU78JzsvhSnBdM8BQp4PwUhRIxz37tv3WfiAUVxOVMME
U21/e+Oq0dFwBdCsx8G7ZRNP0xfWz8dvujo1cVZPWfFHAyBecgkcDQM1shHB4kGt
PRrN3UfS6JOLQ6yBbXWSMMA7sWxZ7dlME7OPvUs3rql/mk20+xzpFJiyXVyMTEGA
uu2l0iSpdwytisYTe2Pn8efwvuG1pIvNYmWIFcBjQIXfRTr0X9UGmGfgXTHlWERL
91BR7wcKvQveMRYYbRdYvHLm/wcCc3o+MhS1My5TZItxZPLFIaZZyvf/Z4gvj9U=
=xJOf
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'stefanha/tags/net-pull-request' into staging
Net patches
# gpg: Signature made Mon 27 Jan 2014 14:45:35 GMT using RSA key ID 81AB73C8
# gpg: Can't check signature: public key not found
* stefanha/tags/net-pull-request:
tap-linux: Get features once and use it many times
Fix lan9118 buffer length handling
Fix lan9118 TX "CMD A" handling
net: Use g_strdup_printf instead of snprintf.
Message-id: 1390834129-19625-1-git-send-email-stefanha@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The following commit:
commit 149f54b53b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: Fri May 24 12:59:37 2013 +0200
memory: add address_space_translate
breaks Xen support in QEMU, in particular the Xen mapcache. The effect
is that one Windows XP installation out of ten would end up with BSOD.
The reason is that after this commit l in address_space_rw can span a
page boundary, however qemu_get_ram_ptr still calls xen_map_cache asking
to map a single page (if block->offset == 0).
Fix the issue by reverting to the previous behaviour: do not return a
length from address_space_translate_internal that can span a page
boundary.
Also in address_space_translate do not ignore the length returned by
address_space_translate_internal.
This patch should be backported to QEMU 1.6.x.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: Anthony Perard <anthony.perard@citrix.com>
Tested-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-stable@nongnu.org
We have cache pools of temporaries that we can reuse later when they've
already been allocated before.
These cache pools differenciate between the target TCG variable type they
contain. So we have one pool for I32 and one pool for I64 variables.
On a 32bit system, we can't work with 64bit registers though. So instead we
spawn two I32 temporaries for every I64 temporary we create. All caching
works the same way as on a real 64-bit system though: We create a cache entry
in the 64bit array for the first i32 index.
However, when we free such a temporary we free it to the pool of its type
(which is always i32 on 32bit systems) rather than its base_type (which is
i64 or i32 depending on the variable). This means we put a temporary that
is of base_type == i64 into the i32 preallocated temporary pool.
Eventually, this results in failures like this on 32bit hosts:
qemu-system-ppc64: tcg/tcg.c:515: tcg_temp_new_internal: Assertion `ts->base_type == type' failed.
This patch makes the free routine use the base_type instead for the free case,
so it's consistent with the temporary allocation. It fixes the above failure
for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1390146811-59936-1-git-send-email-agraf@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
In case monitor_flush() fails to write the contents of mon->outbuf to
the output device, mon->outbuf is not cleaned up properly. Check the
return code of the qemu_chr_fe_write() function and cleanup the outbuf
if it fails.
References: http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02890.html
Signed-off-by: Stratos Psomadakis <psomas@grnet.gr>
Signed-off-by: Dimitris Aragiorgis <dimara@grnet.gr>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
in addition fix default backend leak by releasing it if its
initialization failed.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Introduces USER_CREATABLE interface that must be implemented by
objects which are designed to created with -object CLI option or
object-add QMP command.
Interface provides an ability to do an optional second stage
initialization of the object created with -object/object-add
commands. By providing complete() callback, which is called
after the object properties were set.
It allows to:
* prevents misusing of -object/object-add by filtering out
objects that are not designed for it.
* generalize second stage backend initialization instead of
adding custom APIs to perform it
* early error detection of backend initialization at -object/
object-add time rather than through a proxy DEVICE object
that tries to use backend.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
