Also add various peripherals: two miscellaneous Nokia CBUS chips,
EPSON S1D13745 LCD/TV remote-framebuffer controller,
TWL92230 - standard OMAP2 power management companion chip on i2c.
Generic OneNAND flash memory,
TMP105 temperature sensor on i2c.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4215 c046a42c-6fe2-441c-8c8c-71466251a162
Add also a facility for setting up touchscreen calibration data per-board
based on calibration data generated by tslib.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4214 c046a42c-6fe2-441c-8c8c-71466251a162
Add the OMAP242x (arm1136 core) initialisation with basic on-chip
peripherals and update OMAP1 peripherals which are re-used in OMAP2.
Make palmte.c and sd.c errors go to stderr.
Allow disabling SD chipselect.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
- 0xab is actually a keyboard reply. It should not be escaped.
- Because of translated value 0x41, translated to raw conversion is not
a bijection. Instead of creating two translation tables, test for
s->translate before writing this value.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4209 c046a42c-6fe2-441c-8c8c-71466251a162
When the card is stopped, it should always accept packets, and then
discard them. Thanks to Paul Brook for the explanations.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4128 c046a42c-6fe2-441c-8c8c-71466251a162
Previously, the BIOS would probe the CPUs for SMP guests. This tends to be
very unreliably because of startup timing issues. By passing the number of
CPUs in the CMOS, the BIOS can detect the number of CPUs much more reliably.
(Anthony Liguori)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4114 c046a42c-6fe2-441c-8c8c-71466251a162
* Clean up the interrupt handling a bit.
* Connect some NOR flash to the test board.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4055 c046a42c-6fe2-441c-8c8c-71466251a162
- whole nvram was erased in some conditions
- fix out of range accesses
- improve reading speed by keeping contents in memory
- rename capacity to chip_size
(Hervé Poussineau)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4051 c046a42c-6fe2-441c-8c8c-71466251a162
This patch fixes endianness issues in the e1000 nic emulation, which
currently only works on little endian hosts with little endian targets.
Byte swapping does not depend on host endianness, so this patch remove
the use of cpu_to_le32 and le32_to_cpu functions. It depends on the path
from the CPU to the device, which is currently and *wrongly* implemented
in Qemu as a byteswap on big endian targets. This patch does the same
as in other devices emulation as all the currently implemented targets
work with this implementation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4046 c046a42c-6fe2-441c-8c8c-71466251a162
On big endian targets with mmio accesses, the values are not always
swapped, depending on the accessed register. The Linux 8139too module
was able to cope with that, but not the 8139cp one.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4045 c046a42c-6fe2-441c-8c8c-71466251a162
- Byte swapping for internal GT64XXX registers is controlled by the bit
12 of the Configuration Register and not by the PCI Internal Command
register.
- The bit 0 of the PCI Internal Command register controls byte swapping
for PCI access *except for the internal PCI device*, that is when both
bus and device numbers are 0.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4035 c046a42c-6fe2-441c-8c8c-71466251a162
According to the Intel 82540EM manual, the mmio space is
128k size.
Copied from Xen list and noted by tina..yang@oracle.com
Signed-off-by: Dor Laor <dor.laor@qumranet.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4032 c046a42c-6fe2-441c-8c8c-71466251a162
