It turns out, we're never reading from the signalfd() which is causing it to
remain readable forever. I'll fix this up but I thought I'd commit this fix
in the interim.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5194 c046a42c-6fe2-441c-8c8c-71466251a162
This patch introduces signalfd() to work around the signal/select race in
checking for AIO completions. For platforms that don't support signalfd(), we
emulate it with threads.
There was a long discussion about this approach. I don't believe there are any
fundamental problems with this approach and I believe eliminating the use of
signals is a good thing.
I've tested Windows and Linux using Windows and Linux guests. I've also checked
for disk IO performance regressions.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5187 c046a42c-6fe2-441c-8c8c-71466251a162
This patch removes "BlockDriverState *bs" from nbd_negotiate() because
it is not used.
Signed-off-by: Laurent Vivier <Laurent.Vivier@bull.fr>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5186 c046a42c-6fe2-441c-8c8c-71466251a162
While QEMU officially uses SVN, there are a number of unofficial git
repositories that many developers use. Adding a .gitignore (derived from the
svn:ignore) will make their lives a lot easier.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5183 c046a42c-6fe2-441c-8c8c-71466251a162
As discussed in
http://lists.gnu.org/archive/html/qemu-devel/2008-08/msg00667.html,
current pxe boot is broken for some use cases. The problem
goes away if we reduce the number of allowed bits in the address space
to 32 (which has the side effect of reducing guest max mem size to 4Gb).
After digging for a while, it turns out that it happens because pxelinux
tries to access address 0x10009e9a6, which does not fit a 32-bit address.
A closer look, however, reveals this access is totally valid: It's just
0x9e9a6 with an add carry.
To avoid this, this patch casts the address passed to the POPL macro to
a 32-bit value. This is also done, although just theorectically, for
PUSHL too.
Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Reported-by: Chris Lalancette <clalance@redhat.com>
CC: Eduardo Habkost <ehabkost@redhat.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5182 c046a42c-6fe2-441c-8c8c-71466251a162
- some vectors can be declared as "const"
- test on CONFIG_VNC_TLS is done for two times while just one is enough.
(Carlo Bramini)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5172 c046a42c-6fe2-441c-8c8c-71466251a162
The CMOV instruction is defined by the alpha manual as:
CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format
Operation:
IF TEST(Rav, Condition_based_on_Opcode) THEN
Rc ← Rbv
The current qemu behavior inverses Ra and Rb. This is fixed by this
patch.
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5167 c046a42c-6fe2-441c-8c8c-71466251a162
This patch fixes TCG errors reported on the CRIS target when TCG_DEBUG
is enabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar@axis.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5165 c046a42c-6fe2-441c-8c8c-71466251a162
This patch fixes TCG errors reported on the MIPS target when TCG_DEBUG
is enabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Thiemo Seufer <ths@networkno.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5164 c046a42c-6fe2-441c-8c8c-71466251a162
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].
For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
* Correct numeric value for the RST state.
* Add emulation for reseting a DMA channel.
* Add a few sanity checks.
* Make it compile with debug enabled.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5147 c046a42c-6fe2-441c-8c8c-71466251a162
