Commit Graph

10 Commits

Author SHA1 Message Date
Brian Cain
20c34a9216 target/hexagon: fix some occurrences of -Wshadow=local
Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()`
are less obvious.  They are required because of some macro invocations like
SCATTER_OP_WRITE_TO_MEM().

e.g.:

    In file included from ../target/hexagon/op_helper.c:31:
    ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local]
      205 |         for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
          |                  ^
    ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’
      157 |                 SCATTER_OP_WRITE_TO_MEM(uint16_t);
          |                 ^~~~~~~~~~~~~~~~~~~~~~~
    ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here
      135 |     int i;
          |         ^
    In file included from ../target/hexagon/op_helper.c:31:
    ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local]
      204 |         uintptr_t ra = GETPC(); \
          |                   ^~
    ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’
      160 |                 SCATTER_OP_WRITE_TO_MEM(uint32_t);
          |                 ^~~~~~~~~~~~~~~~~~~~~~~
    ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here
      134 |     uintptr_t ra = GETPC();
          |               ^~

Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231008220945.983643-3-bcain@quicinc.com>
2023-10-18 16:56:17 -07:00
Marco Liebel
3fd49e2217 Hexagon (target/hexagon) Fix assignment to tmp registers
The order in which instructions are generated by gen_insn() influences
assignment to tmp registers. During generation, tmp instructions (e.g.
generate_V6_vassign_tmp) use vreg_src_off() to determine what kind of
register to use as source. If some instruction (e.g.
generate_V6_vmpyowh_64_acc) uses a tmp register but is generated prior
to the corresponding tmp instruction, the vregs_updated_tmp bit map
isn't updated in time.

Exmple:
    { v14.tmp = v16; v25 = v14 } This works properly because
    generate_V6_vassign_tmp is generated before generate_V6_vassign
    and the bit map is updated.

    { v15:14.tmp = vcombine(v21, v16); v25:24 += vmpyo(v18.w,v14.h) }
    This does not work properly because vmpyo is generated before
    vcombine and therefore the bit map does not yet know that there's
    a tmp register.

The parentheses in the decoding function were in the wrong place.
Moving them to the correct location makes shuffling of .tmp vector
registers work as expected.

Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230522174708.464197-1-quic_mliebel@quicinc.com>
2023-05-26 07:03:41 -07:00
Taylor Simpson
f128c0fe10 Hexagon (target/hexagon) Add v68 HVX instructions
The following instructions are added
    V6_v6mpyvubs10_vxx
    V6_v6mpyhubs10_vxx
    V6_v6mpyvubs10
    V6_v6mpyhubs10

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-5-tsimpson@quicinc.com>
2023-05-18 12:40:51 -07:00
Markus Armbruster
1beb07ca8a target/hexagon: Clean up includes
This commit was created with scripts/clean-includes.

All .c should include qemu/osdep.h first.  The script performs three
related cleanups:

* Ensure .c files include qemu/osdep.h first.
* Including it in a .h is redundant, since the .c  already includes
  it.  Drop such inclusions.
* Likewise, including headers qemu/osdep.h includes is redundant.
  Drop these, too.

Changes to standalone programs dropped, because these intentionally
don't use qemu/osdep.h:

    target/hexagon/gen_dectree_import.c
    target/hexagon/gen_semantics.c
    target/hexagon/idef-parser/idef-parser.h
    target/hexagon/idef-parser/parser-helpers.c
    target/hexagon/idef-parser/parser-helpers.h

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20230202133830.2152150-14-armbru@redhat.com>
2023-02-08 07:28:05 +01:00
Taylor Simpson
1e536334cc Hexagon (target/hexagon) Add pkt and insn to DisasContext
This enables us to reduce the number of parameters to many functions
In particular, the generated functions previously took all 3 as arguments

Not only does this simplify the code, it improves the translation time

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20221108162906.3166-2-tsimpson@quicinc.com>
2022-12-16 10:10:28 -08:00
Zongyuan Li
4a818b3767 target/hexagon: remove unused variable
When building with clang version 13.0.0 (eg. Fedora 13.0.0-3.fc35),
two unused variables introduced by macro GATHER_FUNCTION and
SCATTER_FUNCTION will cause building process failure due to
[-Werror -Wunused-variable].

Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/831
Message-Id: <20220124064339.56027-1-zongyuan.li@smartx.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2022-03-12 09:14:22 -08:00
Taylor Simpson
60d1180b68 Hexagon HVX (target/hexagon) instruction decoding
Add new file to target/hexagon/meson.build

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03 16:01:36 -05:00
Taylor Simpson
82f8b3dce2 Hexagon HVX (target/hexagon) instruction utility functions
Functions to support scatter/gather
Add new file to target/hexagon/meson.build

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03 16:01:30 -05:00
Taylor Simpson
64458f4855 Hexagon HVX (target/hexagon) macros
macros to interface with the generator
macros referenced in instruction semantics

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03 16:01:28 -05:00
Taylor Simpson
a1559537d1 Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
HVX is a set of wide vector instructions.  Machine state includes
    vector registers (VRegs)
    vector predicate registers (QRegs)
    temporary registers for intermediate values
    store buffer (masked stores and scatter/gather)

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03 16:01:26 -05:00