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2 Commits

Author SHA1 Message Date
Petar Jovanovic eec8972a5b target-mips: Fix incorrect reads and writes to DSPControl register 
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used in
the MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32
these bits must be written as zero, and return zero on read.

The change fixes writes (WRDSP) and reads (RDDSP) to the register. It also fixes
the tests that use these instructions, and makes them smaller and simpler.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2013-01-01 11:10:47 +01:00
Jia Liu d70080c4e3 target-mips: Add ASE DSP testcases 
Add MIPS ASE DSP testcases.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2012-10-31 21:37:21 +01:00