Commit Graph

514 Commits

Author SHA1 Message Date
Andreas Färber
0ecb72a588 target-arm: Don't overuse CPUState
Scripted conversion:
  sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc]
  sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-14 22:20:24 +01:00
Andreas Färber
1bba0dc932 Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).

Don't hide the parameter type behind explicit casts, use static
functions with strongly typed argument to indirect.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:24 +01:00
Stefan Weil
853bfcc71a target-arm: Clean includes
Remove some include statements which are not needed.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-28 22:33:42 +01:00
Peter Maydell
a84fac1426 target-arm/helper.c: tb_flush() on CPU reset
Since target-arm has some CPUState fields for which we take the approach
of baking assumptions about them into translated code and then calling
tb_flush() when the fields change, we must also tb_flush on CPU reset,
because reset is a change of those fields.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2012-02-17 08:34:43 +01:00
Peter Maydell
2d2624a001 target-arm/helper.c: Correct FPSID value for Cortex-A9
The correct FPSID for the Cortex-A9 (according to the TRM) is
0x41033090 for the r0p0 that we claim to model.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2012-02-17 08:15:06 +01:00
Peter Maydell
0b03bdfca1 Add Cortex-A15 CPU definition
Add a definition of a Cortex-A15 CPU. Note that for the moment we do
not implement any of:
 * Large Physical Address Extensions (LPAE)
 * Virtualization Extensions
 * Generic Timer
 * TrustZone (this is also true of our existing Cortex-A9 model, etc)

This CPU model is sufficient to boot a Linux kernel which has been
compiled for an A15 without LPAE enabled.

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25 15:10:17 +00:00
Peter Maydell
0383ac006f Add dummy implementation of generic timer cp15 registers
Add a dummy implementation of the cp15 registers for the generic
timer (found in the Cortex-A15), just sufficient for Linux to
decide that it can't use it. This requires at least CNTP_CTL and
CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14.

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25 12:42:29 +00:00
Mark Langsdorf
5fe91019e6 arm: store the config_base_register during cpu_reset
Long term, the config_base_register will be a QDM parameter. In the
meantime, models that use it need to be able to preserve it across
cpu_reset() calls.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25 11:49:46 +00:00
Peter Maydell
8583697905 target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
In the helper routines for VCVT float-to-int conversions, add
an explicit cast rather than relying on the softfloat int32
type being exactly 32 bits wide (which it is not guaranteed to be).
Without this, if the softfloat type was 64 bits wide we would
get zero-extension of the 32 bit value from the ARM register
rather than sign-extension, since TCG i32 values are passed as
uint32_t.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25 11:49:46 +00:00
Peter Maydell
dc8714ca57 target-arm: Fix implementation of TLB invalidate operations
Fix some bugs in the implementation of the TLB invalidate
operations on ARM:
 * the 'invalidate all' op was not passing flush_global=1
   to tlb_flush(); this doesn't have a practical effect since
   tlb_flush() currently ignores that argument, but is
   semantically incorrect
 * 'invalidate by address for all ASIDs' was implemented as
   flushing the whole TLB, which invalidates much more than
   strictly necessary. Use tlb_flush_page() instead.
We also annotate the ops with the ARM ARM official acronyms.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25 11:49:46 +00:00
Rob Herring
2be2762421 arm: Add dummy support for co-processor 15's secure config register
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-13 17:25:08 +00:00
Peter Maydell
d3cb6e2b06 target-arm: Fix errors in decode of M profile CPS
Fix errors in the decode of M profile CPS:
 * the decode of the I (affects PRIMASK) and F (affects FAULTMASK)
   bits was reversed
 * the FAULTMASK system register number is 19, not 17

This fixes an issue reported as LP:913925.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-13 17:25:08 +00:00
Mark Langsdorf
7da362d016 arm: add dummy A9-specific cp15 registers
Add dummy register support for the cp15, CRn=c15 registers.

config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05 15:49:06 +00:00
Peter Maydell
37064a8b6f target-arm: Ignore attempts to set invalid modes in CPSR
Ignore attempts to set the CPSR mode field to an invalid value.
This is UNPREDICTABLE, but we should not cpu_abort() for things
a malicious guest (or a confused user on the gdbstub interface)
can provoke.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05 15:49:06 +00:00
Peter Maydell
1b9e01c110 target-arm: Don't use cpu_single_env in bank_number()
Avoid using cpu_single_env in bank_number() -- if we were
called via the gdb stub reading or writing the CPSR then
it is NULL and we will segfault if we take the cpu_abort().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05 15:49:06 +00:00
Andreas Färber
db8336cd1f target-arm: Infer VFPv3 feature from VFPv4
VFP4 => VFP3

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:25 +00:00
Andreas Färber
86e72db6aa target-arm: Infer VFP feature from VFPv3
VFP3 => VFP

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:24 +00:00
Andreas Färber
908ce98085 target-arm: Infer Thumb division feature from M profile
M => THUMB_DIV

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:24 +00:00
Andreas Färber
b3faf5f02e target-arm: Infer Thumb2 feature from ARMv7
V7 => THUMB2

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:24 +00:00
Andreas Färber
10e8770274 target-arm: Infer AUXCR feature from ARMv6
V6 && !M => AUXCR

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:24 +00:00
Andreas Färber
bbc5c5fa17 target-arm: Infer ARMv6(K) feature from ARMv7
V7 && M => V6
V7 && !M => V6K

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:24 +00:00
Andreas Färber
6bf62124f5 target-arm: Infer ARMv6 feature from v6K
V6K => V6

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:24 +00:00
Andreas Färber
08c40f3c62 target-arm: Infer ARMv5 feature from ARMv6
V6 => V5

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:24 +00:00
Andreas Färber
ddb572ec48 target-arm: Infer ARMv4T feature from ARMv5
V5 => V4T

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:23 +00:00
Jean-Christophe DUBOIS
dd4ebc2ecd arm: Fix CP15 FSR (C5) domain setting
Return the correct value in the domain field in the cp15 DFSR
(C5) -- bug noticed during Xvisor development.

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[Peter Maydell: reworded commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13 18:19:23 +00:00
Peter Maydell
f4fc247b0d target-arm/helper.c: Don't allocate TCG resources unless TCG enabled
Don't call arm_translate_init() (which allocates TCG resources)
unless TCG is enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-12-05 21:38:47 +01:00
Peter Maydell
02afbf6475 target-arm/translate.c: Fix slightly misleading comment in Thumb decoder
Clarify some slightly misleading comments in the Thumb decoder's
handling of the memory hint space -- in particular one code path
marked as 'UNPREDICTABLE or unallocated hint' also includes some
legitimate preload instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-12-05 21:38:44 +01:00
Andreas Färber
12b1de3a3f target-arm: Fix use of free() in cpu_arm_close()
env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free().

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-20 14:25:29 +00:00
Dmitry Koshelev
1518025641 target-arm/machine.c: Restore VFP registers correctly
Fix the restoring of VFP registers on vmload.

Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
[peter.maydell: improved commit message a little]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19 16:14:07 +00:00
Peter Maydell
da97f52cb3 target-arm: Implement VFPv4 fused multiply-accumulate insns
Implement the fused multiply-accumulate instructions (VFMA, VFMS,
VFNMA, VFNMS) which are new in VFPv4.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19 16:14:07 +00:00
Peter Maydell
b8b8ea05c4 target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optional
feature for A profile cores (Thumb mode has had UDIV and SDIV for
M profile cores for some time).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19 16:14:06 +00:00
Peter Maydell
477899908f target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to
make room for a new feature switch enabling DIV in the ARM
encoding. (Cores may implement either (a) no divide insns
(b) divide insns in Thumb encodings only (c) divide insns
in both ARM and Thumb encodings.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19 16:14:06 +00:00
Peter Maydell
41e9564df6 target-arm: v6 media multiply space: UNDEF on unassigned encodings
Clean up the decoding of the v6 media multiply space so that we UNDEF
on unassigned encodings rather than randomly interpreting them as
some instruction in this space.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19 16:14:05 +00:00
Christophe LYON
26cc6abf61 rsqrte_f32: No need to copy sign bit.
Indeed, the result is known to be always positive.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19 16:14:05 +00:00
Anthony Liguori
057643f6c4 Merge remote-tracking branch 'stefanha/trivial-patches' into staging 2011-10-10 08:09:02 -05:00
Blue Swirl
6e19a1379d ARM: fix segfault
Fix a bug in bccd9ec5f0,
target-arm/op_helper.c missed a change unlike all other targets.
This lead to a NULL pointer dereferences.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-08 10:00:02 +00:00
Andreas Färber
297d1b4e9d target-arm: Fix typo
The command line option is called -kernel, not -kenrel.

Cc: Paul Brook <paul@codesourcery.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-10-05 09:22:05 +01:00
Blue Swirl
bccd9ec5f0 softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture local
cpu_single_env hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 09:31:26 +00:00
Anthony Liguori
7267c0947d Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-20 23:01:08 -05:00
Edgar E. Iglesias
b9c6cbff76 Merge remote-tracking branch 'pm-arm/for-upstream' into pm 2011-08-09 19:16:43 +02:00
Blue Swirl
97b348e7d2 Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-07 09:32:01 +00:00
Blue Swirl
3e4571724f exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h to
target-*/op_helper.c. Move also various other stuff only used in
op_helper.c there.

Define global env in dyngen-exec.h.

For i386, move wrappers for segment and FPU helpers from user-exec.c
to op_helper.c. Implement raise_exception_err_env() to handle dynamic
CPUState. Move the function declarations to cpu.h since they can be
used outside of op_helper.c context.

LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and
env_to_regs().

ARM: make raise_exception() static.

Convert
#include "exec.h"
to
#include "cpu.h"
#include "dyngen-exec.h"
and remove now unused target-*/exec.h.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 09:41:14 +00:00
Peter Maydell
a492892cbe target-arm: Don't print debug messages for various UNDEF cases
Remove some stray printfs for cases which don't generally happen
(some VFP UNDEF cases, reads and writes to unknown cp14 registers);
we should simply generate an UNDEF when the instruction is executed.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26 14:30:54 +00:00
Peter Maydell
6e0c0ed185 target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assert
VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF.
This avoids a TCG assert later when the VCVTT/VCVTB code tries to
use a source register that wasn't ever set up.

We pull the check for the presence of the half-precision extension
up in to this common code as well.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26 14:30:54 +00:00
Peter Maydell
934814f198 target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM
Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. In
particular, we now generate an undef exception for overlarge imm8
values rather than generating 1000+ TCG ops and hitting an assertion.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26 14:30:54 +00:00
Peter Maydell
87f19eb2a5 target-arm: Support v6 barriers in linux-user mode
ARMv6 implemented various operations as special cases of cp15 accesses
which are true instructions in v7; this includes barriers (DMB, DSB, ISB).
Catch this special case at translate time, so that it works in linux-user
mode (which doesn't provide a functional get_cp15 helper) as well as
system mode.

Includes minor cleanup of the existing cases (single switch statement,
and doing the "OK in user mode?" test explicitly rather than hiding it in
cp15_user_ok()).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26 14:30:54 +00:00
Peter Maydell
906879a98f target-arm: Mark 1136r1 as a v6K core
The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such,
thus enabling the TLS registers, NOP hints, CLREX, half and byte wide
exclusive load/stores, etc.

The VA-to-PA translation registers are not present on 1136r1, so
introduce a new feature flag for them, which is enabled on 1176,
11MPCore and all v7 cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
2011-07-26 14:30:54 +00:00
Jamie Iles
7807eed932 target-arm: support for ARM1176JZF-s cores
Add support for v6K ARM1176JZF-S.  This core includes the VA<->PA
translation capability and security extensions.

Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26 14:30:54 +00:00
Jamie Iles
0ab06d8347 target-arm: make VMSAv7 remapping and AP dependent on V6K
The VMSAv7 remapping and access permissions were introduced in ARMv6K
and not ARMv7.

Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26 14:22:31 +00:00
Matthew Fernandez
8e31bf388e Correct spelling of licensed
Correct typos of "licenced" to "licensed".

Reviewed-by: Stefan Weil <weil@mail.berlios.de>
Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de>
Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-23 11:26:12 -05:00