Commit Graph

75 Commits

Author SHA1 Message Date
Richard Henderson
25c4d9cc84 tcg: Always define all of the TCGOpcode enum members.
By always defining these symbols, we can eliminate a lot of ifdefs.

To allow this to be checked reliably, the semantics of the
TCG_TARGET_HAS_* macros must be changed from def/undef to true/false.
This allows even more ifdefs to be removed, converting them into
C if statements.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:24 +00:00
Aurelien Jarno
244b1e81f6 tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16
instructions on ARMv6+ or shifts and logical operations on previous
ARM versions. In both cases the result use less instructions than
the pure TCG version.

These ops are also needed by the qemu_ld/st functions.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
9517094f72 tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or two
shifts on previous ARM versions. In both cases the result use the same
number or less instructions than the pure TCG version.

Also move all sign extension code to separate functions, so that they
can be reused in other parts of the code.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
293579e55c tcg/arm: add rotation ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
2488b41bb2 tcg/arm: align 64-bit arguments in function calls
As specified by the "Procedure Call Standard for the ARM Architecture".

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
e4a7d5e88c tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that are
clobbered or reserved one by one. This makes the code easier to read.

Also declare all the 16 registers to TCG, and mark pc as reserved.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Richard Henderson
32d98fbd10 tcg: Allow target-specific implementation of NOR.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:52:44 +01:00
Richard Henderson
9940a96bc8 tcg: Allow target-specific implementation of NAND.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:44:40 +01:00
Richard Henderson
8d625cf1d1 tcg: Allow target-specific implementation of EQV.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:42:46 +01:00
Paolo Bonzini
a63b5829af remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 20:48:30 +01:00
Aurelien Jarno
2b71cd72d3 tcg/arm: use helpers for divu/remu
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14 22:04:54 +01:00
Aurelien Jarno
31d6655100 tcg: add div/rem 32-bit helpers
Some targets like ARM would benefit to use 32-bit helpers for
div/rem/divu/remu.

Create a #define for div2 so that targets can select between
div, div2 and helper implementation. Use the helper version if none
of the #define are present.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14 22:04:50 +01:00
Aurelien Jarno
932234f64c tcg/arm: implement andc op
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:46:08 +01:00
Aurelien Jarno
d3f137e355 tcg/arm: merge the two sets of #define for optional ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02 23:12:42 +01:00
Richard Henderson
3682825669 tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:35:12 +00:00
Laurent Desnogues
f878d2d235 ARM back-end: Add TCG not
this patch:

 - implements TCG not.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-22 13:55:06 +02:00
Laurent Desnogues
cb4e581fae this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A
- implement add/sub/and/or/xor with immediate (only 8-bit)

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-07-18 14:20:30 +02:00
Paul Brook
379f6698d7 Userspace guest address offsetting
Re-implement GUEST_BASE support.
Offset guest ddress space by default if the guest binary contains
regions below the host mmap_min_addr.
Implement support for i386, x86-64 and arm hosts.

Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-17 13:12:41 +01:00
Paul Brook
2d69f3590d ARM host fixes
Minor TCG cleanups and warning fixes for ARM hosts.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-17 11:21:12 +01:00
aurel32
66896cb803 tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:34:48 +00:00
blueswir1
e63d7abdde Prune unused TCG_AREGs
Remove definitions for TCG_AREGs corresponding to AREG definitions
removed in r6778.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08 14:45:45 +00:00
balrog
3233f0d463 Use libgcc __clear_cache to clean icache, when available.
Calling the clear cache syscall directly generates an illegal instruction 
on some (armv4) kernels.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5843 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-01 02:02:37 +00:00
balrog
bedba0cd07 Define TCG_TARGET_CALL_STACK_OFFSET on arm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4541 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-23 12:47:22 +00:00
balrog
650bbb361e Implement neg_i32, clean-up.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-20 11:26:40 +00:00
balrog
811d4cf4b0 ARM host support for TCG targets.
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-19 23:59:38 +00:00