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77fcd0934a
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75 Commits

Author SHA1 Message Date
blueswir1
77fcd0934a Fix stack offsets and alignment 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4559 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 16:41:17 +00:00
blueswir1
64e3257c03 Define stack offsets 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4554 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 05:36:16 +00:00
pbrook
bcb0126ff4 More TCGv type fixes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4553 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 02:24:25 +00:00
pbrook
cb63669a54 Fix ARM conditional branch bug. 
Add tcg_gen_brcondi.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 02:22:00 +00:00
balrog
91a3c1b00d Comment non-obvious calculation. Don't clobber r3 in qemu_st64. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4548 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 18:51:15 +00:00
balrog
e936243aca A branch insn must not overwrite the branch target before relocation. 
When a branch to label is translated it generates a reloc that is filled in
when the label is translated.  However, when handling an exception and
searching for the pc we abort the translation early and we sometimes
translate the branch but not the corresponding label and so no relocation
is done.  When the block is executed again the branch points to no-where.

It seems tcg/sparc/ is going to suffer from the same issue.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4547 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 18:50:44 +00:00
bellard
e8996ee012 added tcg_temp_free() and improved the handling of constants 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4544 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 17:33:39 +00:00
balrog
225b437649 Fix qemu_ld/st for mem_index > 0 on arm host. 
offsetof(CPUState, tlb_table[mem_index][0].addr_read) with mem_index > 0
was larger than max immediate offset for ldr and str (12-bit) so insert an
additional insn to add the mem_index offset.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4542 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 12:55:11 +00:00
balrog
bedba0cd07 Define TCG_TARGET_CALL_STACK_OFFSET on arm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4541 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 12:47:22 +00:00
bellard
24bf7b3a1d compilation fix 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4540 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 11:58:32 +00:00
bellard
a23a9ec615 profiler clean up 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4537 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 09:52:20 +00:00
bellard
7e4597d7ae added debug_insn_start debug instruction 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4531 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 16:56:05 +00:00
bellard
4dc81f2822 debug output: write helper names 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4529 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 16:08:32 +00:00
bellard
39cf05d322 more generic call codegen 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4528 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 14:59:57 +00:00
bellard
cf60bce405 fixed zero shifts (64 bit case) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4527 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 14:39:25 +00:00
bellard
34151a20ea small shift opts 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4525 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 13:25:14 +00:00
bellard
e5097dc8e3 fixed dead global variable update 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4512 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-21 16:24:20 +00:00
balrog
204c1674ef Fix 8-bit signed load/store and a typo. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4504 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-20 11:28:35 +00:00
balrog
650bbb361e Implement neg_i32, clean-up. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-20 11:26:40 +00:00
balrog
a2a64a1f2d Remove dyngen ARM code, which did't build. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4501 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-20 00:01:55 +00:00
balrog
811d4cf4b0 ARM host support for TCG targets. 
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-19 23:59:38 +00:00
blueswir1
c44f945a92 Better solution for the alignment problem 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4498 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-19 16:32:18 +00:00
ths
48d38ca52b Switch most MIPS logical and arithmetic instructions to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4496 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 22:50:49 +00:00
blueswir1
57e49b4074 Fix constant checks on Sparc64 host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4486 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 08:11:14 +00:00
blueswir1
d4929d58a1 Fix TCG alignment problems on Sparc64 host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4485 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 07:49:05 +00:00
bellard
c6e113f568 added 'pure' function attribute - fixed indirect function calls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4469 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-17 12:42:15 +00:00
bellard
0b6ce4cffe added not pseudo op - more _tl macros 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4468 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-17 12:40:44 +00:00
blueswir1
9a7f32283c Fix qemu_ld/st branches, constification, use orcc for tst synthetic op 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4466 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-17 09:41:14 +00:00
blueswir1
f5ef6aacd4 Implement qemu_ld/st, fix brcond, handle more corner cases 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4463 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-16 20:15:58 +00:00
blueswir1
cf7c2ca5ff Implement brcond, ldst with large offset; fix direct jump, prologue 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4461 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-15 19:44:09 +00:00
blueswir1
f02ca5cbea Fix bit fitting checks 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4460 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-15 17:30:17 +00:00
blueswir1
7d55170268 Fix compilation on Sparc host, implement ld and st 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4457 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-14 19:22:05 +00:00
bellard
6a8d7b7637 temporary hack to handle register shortage with dyngen for qemu_st64() 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4438 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-12 13:49:14 +00:00
pbrook
390efc54fb Add TCG native negation op. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-11 14:35:37 +00:00
pbrook
868314358e Add zero extension (pseudo-)ops. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-11 12:22:01 +00:00
bellard
3375984648 REXB optimization cannot be done at this level 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4420 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 21:58:28 +00:00
bellard
3c3a1d200c fixed qemu_st8 insn - prologue saved too many registers 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4418 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 21:42:05 +00:00
pbrook
9815642347 Fix DEBUG_TCGV. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4415 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 18:43:02 +00:00
blueswir1
bf6247fb76 Rename CONFIG_NO_DYNGEN_OP to CONFIG_DYNGEN_OP to avoid double negatives 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4412 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 12:27:33 +00:00
bellard
b03cce8e08 fixed global variable handling with qemu load/stores - initial global prologue/epilogue implementation 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4406 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 10:52:05 +00:00
balrog
c7b76a0ae3 Fix i64 remainder calculation copy-paste error. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4357 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-06 14:40:28 +00:00
ths
f730fd27b8 Add helpers and shorthands for mul and muli operations. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4319 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-04 08:14:08 +00:00
blueswir1
4d07272d80 Skip register moves when the target and the source are the same 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4312 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-03 20:52:26 +00:00
aurel32
f54b3f920f HPPA (PA-RISC) host support 
(Stuart Brady)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-12 20:14:54 +00:00
aurel32
ca10f86763 Remove osdep.c/qemu-img code duplication 
(Kevin Wolf)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-11 21:35:42 +00:00
pbrook
b010980544 ARM TCG conversion 9/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:47:03 +00:00
pbrook
6ddbc6e4cf ARM TCG conversion 7/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:46:33 +00:00
blueswir1
e429073d4e Add TL variants of trunc and ext/extu 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4099 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-22 08:39:04 +00:00
blueswir1
cf2be98437 Prepare for op.c removal and zero legacy ops 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4095 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-21 18:03:09 +00:00
blueswir1
fb50d4134d Make TCG br op available 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4093 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-21 17:58:45 +00:00