* Bit swap insn (bitwise not, endian swap and bit reverse).
* Muls and mulu.
* Extended arithmetics.
* Parts of the condition code handling.
* Use tcg_const_tl.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4069 c046a42c-6fe2-441c-8c8c-71466251a162
* Clean up the interrupt handling a bit.
* Connect some NOR flash to the test board.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4055 c046a42c-6fe2-441c-8c8c-71466251a162
- whole nvram was erased in some conditions
- fix out of range accesses
- improve reading speed by keeping contents in memory
- rename capacity to chip_size
(Hervé Poussineau)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4051 c046a42c-6fe2-441c-8c8c-71466251a162
When SDL is invisible/minimized, there is no need to keep calling the
VGA refresh 33 times per second. This patch reduces in that case the
rate to 2 times per second, which should be responsive enough for the
un-minimizing event.
(Samuel Thibault)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4050 c046a42c-6fe2-441c-8c8c-71466251a162
The patch below adds isfinite() and isnormal() functions which can
work with float64 type, used when CONFIG_SOFTFLOAT=yes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4048 c046a42c-6fe2-441c-8c8c-71466251a162
The patch below uses the float32 and float64 types instead of the float
and double types in the PPC code. This doesn't change anything when
using softfloat-native as the types are the same, but that helps
compiling the PPC target with softfloat.
It also defines a new union CPU_FloatU in addition to CPU_DoubleU, and
use them instead of identical unions that are defined in numerous
places.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4047 c046a42c-6fe2-441c-8c8c-71466251a162
This patch fixes endianness issues in the e1000 nic emulation, which
currently only works on little endian hosts with little endian targets.
Byte swapping does not depend on host endianness, so this patch remove
the use of cpu_to_le32 and le32_to_cpu functions. It depends on the path
from the CPU to the device, which is currently and *wrongly* implemented
in Qemu as a byteswap on big endian targets. This patch does the same
as in other devices emulation as all the currently implemented targets
work with this implementation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4046 c046a42c-6fe2-441c-8c8c-71466251a162
On big endian targets with mmio accesses, the values are not always
swapped, depending on the accessed register. The Linux 8139too module
was able to cope with that, but not the 8139cp one.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4045 c046a42c-6fe2-441c-8c8c-71466251a162
Qemu 0.9.1 and earlier does not perform range checks for block device
read or write requests, which allows guest host users with root
privileges to access arbitrary memory and escape the virtual machine.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4037 c046a42c-6fe2-441c-8c8c-71466251a162
- Byte swapping for internal GT64XXX registers is controlled by the bit
12 of the Configuration Register and not by the PCI Internal Command
register.
- The bit 0 of the PCI Internal Command register controls byte swapping
for PCI access *except for the internal PCI device*, that is when both
bus and device numbers are 0.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4035 c046a42c-6fe2-441c-8c8c-71466251a162
The patch below fixes the computation of FPSCR_VX and FPSCR_FEX when
using the mtfsf instruction. As stated in the PowerPC manual the mtfsf
instruction can't alter those bit, and thus it should always be
computed.
Acked by Jocelyn Mayer.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4034 c046a42c-6fe2-441c-8c8c-71466251a162
According to the Intel 82540EM manual, the mmio space is
128k size.
Copied from Xen list and noted by tina..yang@oracle.com
Signed-off-by: Dor Laor <dor.laor@qumranet.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4032 c046a42c-6fe2-441c-8c8c-71466251a162
