3 Commits

Author	SHA1	Message	Date
Richard Henderson	526cd4ec01	tcg/ppc: Support 128-bit load/store ... Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	2023-05-30 09:51:11 -07:00
Richard Henderson	b41b43a477	tcg/ppc: Adjust constraints on qemu_ld/st ... The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	2023-05-11 09:53:41 +01:00
Richard Henderson	6893016b90	tcg/ppc: Split out constraint sets to tcg-target-con-set.h ... Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	2021-02-02 12:12:43 -10:00