Commit Graph

361 Commits

Author SHA1 Message Date
Blue Swirl
3b88670664 Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
* 'ppc-next' of git://repo.or.cz/qemu/agraf:
  PPC: move TLBs to their own arrays
  PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type
  PPC: E500: Use MAS registers instead of internal TLB representation
  PPC: Only set lower 32bits with mtmsr
  PPC: update openbios firmware
  PPC: mpc8544ds: Add hypervisor node
  PPC: calculate kernel,initrd,cmdline locations dynamically
  target-ppc: Handle memory-forced I/O controller access
  PPC: E500: Implement reboot controller
2011-07-01 21:12:50 +00:00
Blue Swirl
2b41f10e18 Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:35 +00:00
Alexander Graf
8018dc63aa PPC: Only set lower 32bits with mtmsr
As Nathan pointed out correctly, the mtmsr instruction does not modify
the high 32 bits of MSR. It also doesn't matter if SF is set or not,
the instruction always behaves the same.

This patch moves it a bit closer to the spec.

Reported-by: Nathan Whitehorn <nwhitehorn@freebsd.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17 02:58:31 +02:00
Aurelien Jarno
2c0d18ddd9 target-ppc: remove old CONFIG_SOFTFLOAT #ifdef
target-ppc has been switched to softfloat only long ago, but a
few #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them.

Cc: Alexander Graf <agraf@suse.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 16:07:48 +02:00
Alexander Graf
01662f3e51 PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, but
we're missing on some of the special TLB0-TLB1 handling code and slightly
different TLB modification.

This patch adds support for the FSL style MMU.

Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12 00:24:51 +02:00
Alexander Graf
a5858d7af0 PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currently
selected CPU emulation, we have a feature mask of what exactly the respective
instruction supports.

This feature mask is 64 bits long and we just successfully exceeded those 64
bits. To add more features, we need to think of something.

The easiest solution that came to my mind was to simply add another 64 bits
that we can also match on. Since the comparison is only done on start of the
qemu process to generate an internal opcode calling table, we should be fine
on any performance penalties here.

Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12 00:24:51 +02:00
Scott Wood
90dc881222 monitor: add PPC BookE SPRs
Read them via KVM_GET_SREGS in kvm_arch_get_registers(),
and display them in "info registers".

Also get CR and PID from the existing KVM_GET_REGS.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-09 22:31:37 +02:00
Stefan Weil
e87b7cb0f0 Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commit
d2856f1ad4.
The only reason for parameter searched_pc was
a debug statement in target-i386/translate.c.

Parameter puc was needed by target-sparc until
commit d7da2a1040.

Remove searched_pc from the debug statement and remove both
parameters from the parameter list of gen_pc_load.

As the function name gen_pc_load was also misleading,
it is now called restore_state_to_opc. This new name
was suggested by Peter Maydell, thanks.

v2: Remove last parameter, too, and rename the function.

v3: Fix [] typo in target-arm/translate.c.
    Fix wrong SHA1 object name in commit message (copy+paste error).

Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-20 10:33:59 +02:00
Stefan Weil
4b4a72e556 Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,
so the type casts of pointer to long should be replaced by
type casts of pointer to tcg_target_long (suggested by Blue Swirl).

These changes are needed for build environments where
sizeof(long) != sizeof(void *), especially for w64.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10 00:45:16 +02:00
David Gibson
bb593904c1 Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1
contains both the base address of the encoded size (hashed) page tables.

At present, we interpret the SDR1 value within the address translation
path.  But because the encodings of the size for 32-bit and 64-bit are
different this makes for a confusing branch on the MMU type with a bunch
of curly shifts and masks in the middle of the translate path.

This patch cleans things up by moving the interpretation on SDR1 into the
helper function handling the write to the register.  This leaves a simple
pre-sanitized base address and mask for the hash table in the CPUState
structure which is easier to work with in the translation path.

This makes the translation path more readable.  It addresses the FIXME
comment currently in the mtsdr1 helper, by validating the SDR1 value during
interpretation.  Finally it opens the way for emulating a pSeries-style
partition where the hash table used for translation is not mapped into
the guests's RAM.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:55 +02:00
David Gibson
eaabeef268 Correct ppc popcntb logic, implement popcntw and popcntd
qemu already includes support for the popcntb instruction introduced
in POWER5 (although it doesn't actually allow you to choose POWER5).

However, the logic is slightly incorrect: it will generate results
truncated to 32-bits when the CPU is in 32-bit mode.  This is not
normal for powerpc - generally arithmetic instructions on a 64-bit
powerpc cpu will generate full 64 bit results, it's just that only the
low 32 bits will be significant for condition codes.

This patch corrects this nit, which actually simplifies the code slightly.

In addition, this patch implements the popcntw and popcntd
instructions added in POWER7, in preparation for allowing POWER7 as an
emulated CPU.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:54 +02:00
David Gibson
efdef95fee Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer.  Likewise it supports the
slbmte instruction which is used to load entries into the SLB.

However, it does not emulate the slbmfee and slbmfev instructions
which read SLB entries back into registers.  Because these are
only occasionally used in guests (mostly for debugging) we get
away with it.

However, given the recent SLB cleanups, it becomes quite easy to
implement these, and thereby allow, amongst other things, a guest
Linux to use xmon's command to dump the SLB.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:54 +02:00
Aurelien Jarno
17d9b3af5b target-ppc: ext32u instead of andi with constant
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:37 +02:00
Fabien Chouteau
a0e1390007 target-ppc: add support for 6 SPE instructions
Add support for 6 SPE instructions: evmra, evmwsmi{a{a}}, evmwumi{a{a}}

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22 07:17:16 +01:00
Edgar E. Iglesias
5823947f9f ppc: Correct BookE tlb reads
Call the tlb read helper (and not the write helper) for tlb
reads.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-21 23:12:42 +01:00
Mike Pall
6d5c34fa02 Fix translation of unary PPC/SPE instructions (efdneg etc.).
Signed-off-by: Mike Pall <mike-lp10@luajit.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-31 21:17:53 +01:00
Stefan Weil
9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Alexander Graf
f844c817d7 PPC: Enable hint bits for lwarx/ldarx
The lwarx and ldarx instructions have a bit to give some hint to the
CPU which is safe to ignore. We currently refuse to accept any instruction
with that bit set, as it used to be declared MBZ.

Let's remove the reserved bit and make the instruction work as expected.
This fixes Linux boot for ppc64.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-09-15 16:18:27 +02:00
Aurelien Jarno
0bffbc6c7d target-ppc: add vexptefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-13 18:18:32 +02:00
Blue Swirl
0bfcd599e3 Fix %lld or %llx printf format use
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22 08:02:12 +00:00
Richard Henderson
8d0d2eb6b2 target-ppc: Remove duplicate cpu log.
Logging for -d cpu is done in generic code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05 12:20:05 +02:00
Blue Swirl
05f92404cd ppc: remove dead assignments, spotted by clang analyzer
Value stored is never read.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-25 20:32:49 +00:00
Blue Swirl
7b13448f05 PPC: avoid function pointer type mismatch, spotted by clang
Fixes clang errors:
  CC    ppc-softmmu/translate.o
/src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
        if (likely(read_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3748:28: note: instantiated from:
        if (likely(read_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3903:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
        if (likely(write_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3903:29: note: instantiated from:
        if (likely(write_cb != SPR_NOACCESS)) {

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-18 14:26:51 +00:00
Aurelien Jarno
0aef4261ac target-ppc: fix evsrwu and evsrws (second try)
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11 21:29:42 +01:00
Aurelien Jarno
26b14dc4ab target-ppc: fix evsrwu and evsrws
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11 21:22:35 +01:00
Aurelien Jarno
e29ef9fabe target-ppc: fix evslw instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11 21:14:47 +01:00
Aurelien Jarno
6c71232122 target-ppc: don't print invalid opcode messages on the console
Invalid opcode messages can be perfectly normal, for example if this
code is never executed. Don't print an error message on the console,
but keep the message in the log for debugging purposes.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 16:36:44 +01:00
Aurelien Jarno
db9a231d1f Revert "target-ppc: stop translation after a trap instruction"
This reverts commit 6454e7be1b.
2010-02-28 16:36:44 +01:00
Aurelien Jarno
6454e7be1b target-ppc: stop translation after a trap instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 14:11:06 +01:00
Nathan Froyd
ae01847f9c target-ppc: fix SPE evsplat* instructions
The shifts in the gen_evsplat* functions were expecting rA to be masked,
not extracted, and so used the wrong shift amounts to sign-extend or pad
with zeroes.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-27 16:10:50 +01:00
Anthony Liguori
c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc
99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Aurelien Jarno
731c54f869 target-ppc: log instructions start in TCG code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-28 13:40:12 +02:00
Juan Quintela
86178a576b static and inline should came before the type of the functions
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-25 19:51:45 +00:00
Aurelien Jarno
7fd6bf7dae target-ppc: optimize slw/srw/sld/srd
Remove a temp local variable and a jump by computing a mask with shifts.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-18 16:57:33 +02:00
Blue Swirl
72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Blue Swirl
b11ebf64b6 Replace REGX with PRIx64
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 11:54:37 +00:00
Blue Swirl
90e189ece1 Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 11:13:18 +00:00
Blue Swirl
636aa20056 Replace always_inline with inline
We define inline as always_inline.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 09:06:54 +00:00
Nathan Froyd
4425265beb target-ppc: add exceptions for conditional stores
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Nathan Froyd
18b21a2f83 target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed.  It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Juan Quintela
e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Baojun Wang
fbe73008f2 ppc tcg: fix wrong bit/mask of wrteei
Signed-off-by: Baojun Wang <wangbj@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-13 01:51:17 +02:00
Nathan Froyd
33890b3e0d target-ppc: fix evmergelo and evmergelohi
For 32-bit PPC targets, we translated:

evmergelo rX, rX, rY

as:

rX-lo = rY-lo
rX-hi = rX-lo

which is wrong, because we should be transferring rX-lo first.  This
problem is fixed by swapping the order in which we write the parts of
rX.

Similarly, we translated:

evmergelohi rX, rX, rY

as:

rX-lo = rY-hi
rX-hi = rX-lo

In this case, we can't swap the assignment statements, because that
would just cause problems for:

evmergelohi rX, rY, rX

Instead, we detect the first case and save rX-lo in a temporary
variable:

tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp

These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12 23:36:21 +02:00
malc
d2e9fd8f70 Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be used
uninitialized
2009-06-20 05:51:47 +04:00
Blue Swirl
5c55ff99fa Replace ELF section hack with normal table
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:31 +00:00
Blue Swirl
2e6100507a Concentrate rest of table entries to top
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:24 +00:00
Blue Swirl
5462327761 Concentrate most table entries to top
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:19 +00:00
Blue Swirl
e8eaa2c012 Clean up GEN_HANDLER2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:14 +00:00