Commit Graph

176 Commits

Author SHA1 Message Date
Stefan Weil
9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Chih-Min Chao
ed89a2f1b1 target-arm : fix thumb2 parallel add/sub opcode decoding
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:29 +02:00
Paul Brook
41ba834146 NEON vldN optimization
When combining multiple values as part of a NEON array load, do explcit
shift/or rather than using gen_bfi.  This voids redundant mask
operations.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-06-11 20:37:51 +01:00
Blue Swirl
22ed1d3478 arm: remove dead assignments, spotted by clang analyzer
Value stored is never read.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-25 19:31:06 +00:00
Juha Riihimäki
8e31209eea target-arm: fix neon vmon/vmvn with modified immediate
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com>
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:12:24 +02:00
Lars Munch
d996882703 target-arm: resource leak fixes for iwmmxt disassemble
This patch fixes few resource leaks in the iwmmxt disassemble.

Signed-off-by: Lars Munch <lars@segv.dk>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:11:21 +02:00
Johan Bengtsson
bedd2912c8 target-arm: Fix handling of AL condition in IT instruction
Do not try to insert a conditional jump over next instruction when the
condition code is AL as this will trigger an internal error.

Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23 22:10:45 +01:00
Adam Lackorzynski
ea825eeefd target-arm: make RFE usable with any register
The rfe instruction can be used with any register, not just sp. Adjust the
condition check accordingly.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 12:01:29 +01:00
Adam Lackorzynski
a990f58fed target-arm: Fix missing 'return' in SRS handling.
There's a return missing in the srs handling which leads to srs always being
treated an an invalid op.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06 23:22:22 +01:00
Juha Riihimäki
30d11a2a01 target-arm: neon vshll instruction fix
implementation only widened the 32bit source vector elements into a
64bit destination vector but forgot to perform the actual shifting
operation.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 19:30:56 +01:00
Riku Voipio
79b0e534c0 target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN
The rounding/truncating options were inverted. truncating
was done when rounding was meant and vice verse.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 19:30:04 +01:00
Paul Brook
c5883be235 ARM CP15 tls fix
Fix temporary handling in cp15 tls register load/store.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-23 14:45:16 +00:00
Rabin Vincent
b8b45b68f8 target-arm: implement Thumb-2 exception return
Support the "subs pc, lr" Thumb-2 exception return instruction.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19 13:38:43 +00:00
Rabin Vincent
fa26df032e target-arm: fix thumb CPS
The Thumb CPS currently does not work correctly: CPSID touches more bits
than the instruction wants to, and CPSIE does nothing.  Fix it by
passing the correct mask (the "affect" bits) and value.

Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-19 13:38:32 +00:00
Riku Voipio
3f26c1227e target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled
with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
already checked in cp15_user_ok.

While at it, make the cp15.c13 Thread ID registers available only on
ARMv6K and newer.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-02-06 17:19:43 +01:00
Aurelien Jarno
502e64fe23 target-arm: fix strexd
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-24 00:18:23 +01:00
Paul Brook
426f5abcaa ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-22 21:35:13 +00:00
Paul Brook
600114988c ARM FP16 support
Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19 16:45:20 +00:00
Aurelien Jarno
f669df275c target-arm: use native tcg-ops for ror/bic/vorn
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:27 +01:00
Juha Riihimäki
ca9a32e4f3 target-arm: fix neon vsri, vshl and vsli ops
Shift by immediate value is incorrectly overwritten by a temporary
variable in the processing of NEON vsri, vshl and vsli instructions.
This patch has been revised to also include a fix for the special
case where the code would previously try to shift an integer value
over 31 bits left/right.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
71b3c3dea2 target-arm: allow modifying vfp fpexc en bit only
All other bits except for the EN in the VFP FPEXC register are defined
as subarchitecture specific and real functionality for any of the
other bits has not been implemented in QEMU. However, current code
allows modifying all bits in the VFP FPEXC register leading to
problems when guest code is writing 1's to the subarchitecture
specific bits and checking whether the bits stay up to verify the
existence of functionality which in fact does not exist in QEMU.
This patch has been revised to include the same behavior change in
the gdb register write function.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
8449623376 target-arm: add support for neon vld1.64/vst1.64 instructions
Add support for NEON vld1.64 and vst1.64 instructions. This patch is
revised to follow more closely the specification and raises
undefined exception if 64bit element size is used for vld2/vst2 or
vld4/vst4 instructions.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
2301db4916 target-arm: fix neon vshrn/vrshrn ops
In the existing code shift value is clobbered during the pass loop.
This patch changes the code so that it stores the intermediate
result in the target neon register directly and eliminates the need
to use a temporary to hold the intermediate value thus leaving the
shift value in the temporary variable intact. This is a new patch
in this version of the patch series.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
25aeb69b8d target-arm: fix incorrect temporary variable freeing
tmp4 and tmp5 temporary variables are allocated using tcg_const_i32
but incorrectly released using dead_tmp which will cause resource
leak tracking to report false leaks.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by:  Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-26 20:36:47 +01:00
Juha.Riihimaki@nokia.com
7b2919a0b4 target-arm: optimize thumb 32-bit multiply
Current implementation of thumb mul instruction is implemented as a
32x32->64 multiply which then uses only 32 least significant bits of
the result. Replace that with a simple 32x32->32 multiply.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:22:13 +02:00
Juha Riihimäki
b75263d653 target-arm: cleanup internal resource leaks
Revised patch for getting rid of tcg temporary variable leaks in
target-arm/translate.c. This version also includes the leak patch for
gen_set_cpsr macro, now converted as a static inline function, which I
sent earlier as a separate patch on top of this patch.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:11:43 +02:00
Aurelien Jarno
dcc65026c4 target-arm: fix bugs introduced by 1b2b1e547b
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 16:00:18 +02:00
Aurelien Jarno
98a463171b target-arm: fix bugs introduced by 3174f8e91f
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 15:53:28 +02:00
Filip Navara
747a651e8e target-arm: remove cpu_T for ARM once and for all
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:18 +02:00
Filip Navara
312eea9f99 target-arm: convert VFP not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
da6b5335d5 target-arm: convert disas_iwmmxt_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
3a554c0f20 target-arm: convert disas_dsp_insn not use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
1b2b1e547b target-arm: convert disas_neon_ls_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
dd8fbd787e target-arm: convert disas_neon_data_insn and helpers not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
3174f8e91f target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
396e467cb1 target-arm: replace thumb usage of cpu_T registers by proper register allocations
The goal is eventually to get rid of all cpu_T register usage and to use
just short-lived tmp/tmp2 registers. This patch converts all the places where
cpu_T was used in the Thumb code and replaces it with explicit TCG register
allocation.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
15bb4eac12 target-arm: fix TANDC and TORC instructions
Uninitialized register was used instead of proper TCG variable.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
194576157a target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16
helpers used fixed registers to return values. This patch replaces that with
TCG code, so T0/T1 is no longer directly used by the helper functions.

Bugs in the gen_neon_unzip register load code were also fixed.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
a6445c52aa target-arm: convert gen_lookup_tb not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
2fbac54be0 target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
c67b6b719b target-arm: fix SRS/RFE instructions
The encoding of 'IA' and 'DB' conditions was swapped.
SRS instruction must store banked SPSR instead of CPSR at the specific address.
Missing 'return' statement at the end of RFE handling.
Fixed write-back code to reference correct registers.

From: Hyeonsung Jang <hsjang@ok-labs.com>
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
217aff9c76 target-arm: remove unused gen_movl_T2_reg function
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
288eebe54f target-arm: remove useless line that sets register that is never used again
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
12edd4f269 target-arm: get rid of temporary variable cache
The temporary variable cache in no longer need since tcg_temp_free was introduced.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
155c3eacd2 target-arm: use tcg_global_mem_new_i32 to allocate registers
Currently each read/write of ARM register involves a LD/ST TCG operation. This
patch uses TCG memory-backed registers to represent the ARM register set. With
memory-backed registers the LD/ST operations are transparently generated by TCG
and host registers could be used to optimize the generated code.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Blue Swirl
72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Filip Navara
024589f182 Remove unused gen_bx_T0 function.
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-24 09:09:15 -05:00
Juha Riihimäki
21aeb3430c fix ARMv7 data processing instructions
ARMv7 defines a new behavior for ARM data processing instructions
compared to earlier architecture revisions; when the destination
register is R15, a Branch and Exchange operation is executed rather
than a simple Branch to the target address. This patch corrects the
behavior of the emulation for the aforementioned operations. To be
applied after applying the previous patch in this patch set.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-15 03:18:42 +01:00
Juha Riihimäki
e9bb4aa977 fix ARMv7 data processing instructions
Modernize parts of target-arm/translate.c in preparation for the
modifications in the subsequent patch in this patch set. This is done
in order to avoid writing new code to target-arm/translate.c that
would use deprecated methods and/or variables.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-15 02:48:18 +01:00