Commit Graph

34454 Commits

Author SHA1 Message Date
Thomas Huth
2fb40d1b94 hw/s390x/s390-skeys: Don't call register_savevm_live() during instance_init()
Since the instance_init() function immediately tries to set the
property to "true", the s390_skeys_set_migration_enabled() tries
to register a savevm handler during instance_init(). However,
instance_init() functions can be called multiple times, e.g. for
introspection of devices. That means multiple instances of devices
can be created during runtime (which is fine as long as they all
don't get realized, too), so the "Prevent double registration of
savevm handler" check in the s390_skeys_set_migration_enabled()
function does not work at all as expected (since there could be
more than one instance).

Thus we must not call register_savevm_live() from an instance_init()
function at all. Move this to the realize() function instead. This
way we can also get rid of the property getter and setter functions
completely, simplifying the code along the way quite a bit.

Acked-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Acked-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231020150554.664422-2-thuth@redhat.com>
2023-11-01 16:13:58 +01:00
Thomas Huth
6436db5a60 hw/ipmi: Don't call vmstate_register() from instance_init() functions
instance_init() can be called multiple times, e.g. during introspection
of the device. We should not install the vmstate handlers here. Do it
in the realize() function instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231020145554.662751-1-thuth@redhat.com>
2023-11-01 16:13:58 +01:00
Stefan Hajnoczi
073458da56 virtio-blk: remove batch notification BH
There is a batching mechanism for virtio-blk Used Buffer Notifications
that is no longer needed because the previous commit added batching to
virtio_notify_irqfd().

Note that this mechanism was rarely used in practice because it is only
enabled when EVENT_IDX is not negotiated by the driver. Modern drivers
enable EVENT_IDX.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-ID: <20230913200045.1024233-5-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-10-31 15:42:17 +01:00
Stefan Hajnoczi
84d61e5f36 virtio: use defer_call() in virtio_irqfd_notify()
virtio-blk and virtio-scsi invoke virtio_irqfd_notify() to send Used
Buffer Notifications from an IOThread. This involves an eventfd
write(2) syscall. Calling this repeatedly when completing multiple I/O
requests in a row is wasteful.

Use the defer_call() API to batch together virtio_irqfd_notify() calls
made during thread pool (aio=threads), Linux AIO (aio=native), and
io_uring (aio=io_uring) completion processing.

Behavior is unchanged for emulated devices that do not use
defer_call_begin()/defer_call_end() since defer_call() immediately
invokes the callback when called outside a
defer_call_begin()/defer_call_end() region.

fio rw=randread bs=4k iodepth=64 numjobs=8 IOPS increases by ~9% with a
single IOThread and 8 vCPUs. iodepth=1 decreases by ~1% but this could
be noise. Detailed performance data and configuration specifics are
available here:
https://gitlab.com/stefanha/virt-playbooks/-/tree/blk_io_plug-irqfd

This duplicates the BH that virtio-blk uses for batching. The next
commit will remove it.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-ID: <20230913200045.1024233-4-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-10-31 15:42:14 +01:00
Stefan Hajnoczi
433fcea40c util/defer-call: move defer_call() to util/
The networking subsystem may wish to use defer_call(), so move the code
to util/ where it can be reused.

As a reminder of what defer_call() does:

This API defers a function call within a defer_call_begin()/defer_call_end()
section, allowing multiple calls to batch up. This is a performance
optimization that is used in the block layer to submit several I/O requests
at once instead of individually:

  defer_call_begin(); <-- start of section
  ...
  defer_call(my_func, my_obj); <-- deferred my_func(my_obj) call
  defer_call(my_func, my_obj); <-- another
  defer_call(my_func, my_obj); <-- another
  ...
  defer_call_end(); <-- end of section, my_func(my_obj) is called once

Suggested-by: Ilya Maximets <i.maximets@ovn.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-ID: <20230913200045.1024233-3-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-10-31 15:41:42 +01:00
Stefan Hajnoczi
ccee48aa73 block: rename blk_io_plug_call() API to defer_call()
Prepare to move the blk_io_plug_call() API out of the block layer so
that other subsystems call use this deferred call mechanism. Rename it
to defer_call() but leave the code in block/plug.c.

The next commit will move the code out of the block layer.

Suggested-by: Ilya Maximets <i.maximets@ovn.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Paul Durrant <paul@xen.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-ID: <20230913200045.1024233-2-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-10-31 15:41:24 +01:00
Stefan Hajnoczi
235fe6d06e ufs-next-pull-request
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Merge tag 'pull-ufs-20231030' of https://gitlab.com/jeuk20.kim/qemu into staging

ufs-next-pull-request

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# gpg: Signature made Mon 30 Oct 2023 10:59:22 JST
# gpg:                using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602
# gpg: Good signature from "Jeuk Kim <jeuk20.kim@samsung.com>" [unknown]
# gpg:                 aka "Jeuk Kim <jeuk20.kim@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 5017 D831 597C 78A3 D907  EEF7 12E2 204C 0E5D B602

* tag 'pull-ufs-20231030' of https://gitlab.com/jeuk20.kim/qemu:
  hw/ufs: Modify lu.c to share codes with SCSI subsystem

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-31 07:11:23 +09:00
Stefan Hajnoczi
850e874f1c target-arm queue:
* Correct minor errors in Cortex-A710 definition
  * Implement Neoverse N2 CPU model
  * Refactor feature test functions out into separate header
  * Fix syndrome for FGT traps on ERET
  * Remove 'hw/arm/boot.h' includes from various header files
  * pxa2xx: Refactoring/cleanup
  * Avoid using 'first_cpu' when first ARM CPU is reachable
  * misc/led: LED state is set opposite of what is expected
  * hw/net/cadence_gen: clean up to use FIELD macros
  * hw/net/cadence_gem: perform PHY access on write only
  * hw/net/cadence_gem: enforce 32 bits variable size for CRC
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Merge tag 'pull-target-arm-20231027' of https://git-us.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Correct minor errors in Cortex-A710 definition
 * Implement Neoverse N2 CPU model
 * Refactor feature test functions out into separate header
 * Fix syndrome for FGT traps on ERET
 * Remove 'hw/arm/boot.h' includes from various header files
 * pxa2xx: Refactoring/cleanup
 * Avoid using 'first_cpu' when first ARM CPU is reachable
 * misc/led: LED state is set opposite of what is expected
 * hw/net/cadence_gen: clean up to use FIELD macros
 * hw/net/cadence_gem: perform PHY access on write only
 * hw/net/cadence_gem: enforce 32 bits variable size for CRC

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# gpg: Signature made Fri 27 Oct 2023 23:37:49 JST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20231027' of https://git-us.linaro.org/people/pmaydell/qemu-arm: (41 commits)
  hw/net/cadence_gem: enforce 32 bits variable size for CRC
  hw/net/cadence_gem: perform PHY access on write only
  hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
  hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
  hw/net/cadence_gem: use FIELD to describe IRQ register fields
  hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
  hw/net/cadence_gem: use FIELD to describe DMACFG register fields
  hw/net/cadence_gem: use FIELD to describe NWCFG register fields
  hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
  hw/net/cadence_gem: use FIELD for screening registers
  hw/net/cadence_gem: use REG32 macro for register definitions
  misc/led: LED state is set opposite of what is expected
  hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
  hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
  hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
  hw/intc/pxa2xx: Pass CPU reference using QOM link property
  hw/intc/pxa2xx: Convert to Resettable interface
  hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
  hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
  hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-31 07:07:42 +09:00
Jeuk Kim
096434fea1 hw/ufs: Modify lu.c to share codes with SCSI subsystem
This patch removes the code that ufs-lu was duplicating from
scsi-hd and allows them to share code.

It makes ufs-lu have a virtual scsi-bus and scsi-hd internally.
This allows scsi related commands to be passed thorugh to the scsi-hd.
The query request and nop command work the same as the existing logic.

Well-known lus do not have a virtual scsi-bus and scsi-hd, and
handle the necessary scsi commands by emulating them directly.

Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2023-10-30 10:28:04 +09:00
Stefan Hajnoczi
f09cc2b50c * Fix global variable shadowing in test code
* Avoid recompiling libfdt in the FreeBSD VM
 * Mark old pc machine types as deprecated
 * Force IPv4 in the ipmi-bt-test
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Merge tag 'pull-request-2023-10-27' of https://gitlab.com/thuth/qemu into staging

* Fix global variable shadowing in test code
* Avoid recompiling libfdt in the FreeBSD VM
* Mark old pc machine types as deprecated
* Force IPv4 in the ipmi-bt-test

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# gpg: Signature made Fri 27 Oct 2023 18:33:32 JST
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2023-10-27' of https://gitlab.com/thuth/qemu:
  ipmi-bt-test: force ipv4
  tests/vm/freebsd: Add additional library paths for libfdt
  docs/about: Mark the old pc-i440fx-2.0 - 2.3 machine types as deprecated
  tests/coroutine: Clean up global variable shadowing
  tests/aio: Clean up global variable shadowing
  tests/npcm7xx_adc: Clean up global variable shadowing
  tests/rtl8139: Clean up global variable shadowing
  tests/cdrom-test: Clean up global variable shadowing in prepare_image()
  tests/virtio-scsi: Clean up global variable shadowing
  tests/throttle: Clean up global variable shadowing
  system/qtest: Clean up global variable shadowing in qtest_server_init()

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-30 08:08:18 +09:00
Luc Michel
df93de987f hw/net/cadence_gem: enforce 32 bits variable size for CRC
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-12-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
71a082a3fa hw/net/cadence_gem: perform PHY access on write only
The MDIO access is done only on a write to the PHYMNTNC register. A
subsequent read is used to retrieve the result but does not trigger an
MDIO access by itself.

Refactor the PHY access logic to perform all accesses (MDIO reads and
writes) at PHYMNTNC write time.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-11-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
1b09eeb122 hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
Use the FIELD macro to describe the PHYMNTNC register fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-10-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
ce077875da hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
Use the FIELD macro to describe the DESCONF6 register fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231017194422.4124691-9-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
987e806017 hw/net/cadence_gem: use FIELD to describe IRQ register fields
Use de FIELD macro to describe the IRQ related register fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-8-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
466da85716 hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-7-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
01f9175dbc hw/net/cadence_gem: use FIELD to describe DMACFG register fields
Use de FIELD macro to describe the DMACFG register fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-6-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
87a49c3f80 hw/net/cadence_gem: use FIELD to describe NWCFG register fields
Use de FIELD macro to describe the NWCFG register fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-5-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
bd8a922d2f hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
Use the FIELD macro to describe the NWCTRL register fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-4-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
b46b526c08 hw/net/cadence_gem: use FIELD for screening registers
Describe screening registers fields using the FIELD macros.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-3-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Luc Michel
c755c943aa hw/net/cadence_gem: use REG32 macro for register definitions
Replace register defines with the REG32 macro from registerfields.h in
the Cadence GEM device.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-2-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 15:27:06 +01:00
Glenn Miles
6f83dc6716 misc/led: LED state is set opposite of what is expected
Testing of the LED state showed that when the LED polarity was
set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
the input GPIO of the LED, the LED was being turn off when it was
expected to be turned on.

Fixes: ddb67f6402 ("hw/misc/led: Allow connecting from GPIO output")
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Message-id: 20231024191945.4135036-1-milesg@linux.vnet.ibm.com
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:51:17 +01:00
Philippe Mathieu-Daudé
f0109f721e hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
Prefer using a well known local first CPU rather than a global one.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231025065909.57344-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:50:12 +01:00
Philippe Mathieu-Daudé
bf348bf9ab hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
qbus_new(), called in i2c_init_bus(), should not be called
on unrealized device.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20231020130331.50048-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
25c4ff29d1 hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20231020130331.50048-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
ee5c9b5b19 hw/intc/pxa2xx: Pass CPU reference using QOM link property
QOM objects shouldn't access each other internals fields
except using the QOM API.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20231020130331.50048-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
ead17ebf53 hw/intc/pxa2xx: Convert to Resettable interface
Factor reset code out of the DeviceRealize() handler.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20231020130331.50048-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
cbf08c1851 hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231020130331.50048-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
77d3fa5c30 hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231020130331.50048-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
217ceefee0 hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
sysbus_mmio_map() should not be called on unrealized device.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231020130331.50048-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
d8239c475b hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231020130331.50048-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
85500a1aef hw/sd/pxa2xx: Realize sysbus device before accessing it
sysbus_mmio_map() and sysbus_connect_irq() should not be
called on unrealized device.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231020130331.50048-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:48:57 +01:00
Philippe Mathieu-Daudé
f3205af4c7 hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
d95a3a7580 hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
f27cbd94ee hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
8727076bb9 hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
e77bf48586 hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
88e763dab4 hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
6fda3b91bf hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
6f4d538aa1 hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
0e246c6209 hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Philippe Mathieu-Daudé
0c436de6ba hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20231025065316.56817-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27 12:42:13 +01:00
Peter Maydell
5a534314a8 target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly
a thousand lines in target/arm/cpu.h. This header file is included
by a lot of source files, most of which don't need these functions.
Move the feature test functions to their own header file.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
2023-10-27 11:44:32 +01:00
Peter Maydell
dfff1000fe target/arm: Implement Neoverse N2 CPU model
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A
processor very similar to the Cortex-A710. The differences are:
 * no FEAT_EVT
 * FEAT_DGH (data gathering hint)
 * FEAT_NV (not yet implemented in QEMU)
 * Statistical Profiling Extension (not implemented in QEMU)
 * 48 bit physical address range, not 40
 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed)
 * PMCR_EL0.N = 6 (always 6 PMU counters, not 20)

Because it has 48-bit physical address support, we can use
this CPU in the sbsa-ref board as well as the virt board.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
2023-10-27 11:41:13 +01:00
Thomas Huth
c7437f0ddb docs/about: Mark the old pc-i440fx-2.0 - 2.3 machine types as deprecated
As we've seen in the past, it's useful for deprecating old machine
types to finally be able to get of legacy code or do other clean-ups
(see e.g. commit ea985d235b that was used to drop the PCI code in
the 128k bios binaries to free some precious space in those binaries).

So let's continue deprecating the oldest pc machine types. QEMU 2.3
has been released 8 years ago, so that's plenty of time since such
machine types have been used by default, thus deprecating pc-i440fx-2.0
up to pc-i440fx-2.3 should be fine nowadays.

Message-ID: <20231006075247.403364-1-thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27 09:43:06 +02:00
Stefan Hajnoczi
3c95fd4ed8 * target/i386: implement SHA instructions
* target/i386: check CPUID_PAE to determine 36 bit processor address space
 * target/i386: improve validation of AVX instructions
 * require Linux 4.4 for KVM
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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* target/i386: implement SHA instructions
* target/i386: check CPUID_PAE to determine 36 bit processor address space
* target/i386: improve validation of AVX instructions
* require Linux 4.4 for KVM

# -----BEGIN PGP SIGNATURE-----
#
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# QHJlZGhhdC5jb20ACgkQv/vSX3jHroNVbwf9HCx+C0MITWjQ+rEkmtiy/Cn+ZsF1
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# =WYTo
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 26 Oct 2023 02:53:50 JST
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (24 commits)
  kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2
  kvm: i386: require KVM_CAP_SET_IDENTITY_MAP_ADDR
  kvm: i386: require KVM_CAP_ADJUST_CLOCK
  kvm: i386: require KVM_CAP_MCE
  kvm: i386: require KVM_CAP_SET_VCPU_EVENTS and KVM_CAP_X86_ROBUST_SINGLESTEP
  kvm: i386: require KVM_CAP_XSAVE
  kvm: i386: require KVM_CAP_DEBUGREGS
  kvm: i386: move KVM_CAP_IRQ_ROUTING detection to kvm_arch_required_capabilities
  kvm: unify listeners for PIO address space
  kvm: require KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH
  kvm: assume that many ioeventfds can be created
  kvm: drop reference to KVM_CAP_PCI_2_3
  kvm: require KVM_IRQFD for kernel irqchip
  kvm: require KVM_IRQFD for kernel irqchip
  kvm: require KVM_CAP_SIGNAL_MSI
  kvm: require KVM_CAP_INTERNAL_ERROR_DATA
  kvm: remove unnecessary stub
  target/i386: check CPUID_PAE to determine 36 bit processor address space
  target/i386: validate VEX.W for AVX instructions
  target/i386: group common checks in the decoding phase
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-27 09:43:07 +09:00
Paolo Bonzini
39dd3e1f55 kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25 19:53:38 +02:00
Paolo Bonzini
700766ba60 kvm: i386: require KVM_CAP_ADJUST_CLOCK
This was introduced in KVM in Linux 2.6.33, we can require it
unconditionally.  KVM_CLOCK_TSC_STABLE was only added in Linux 4.9,
for now do not require it (though it would allow the removal of some
pretty yucky code).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25 19:53:38 +02:00
Paolo Bonzini
126e7f7803 kvm: require KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH
KVM_CAP_IOEVENTFD_ANY_LENGTH was added in Linux 4.4, released in 2016.
Assume that it is present.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25 17:35:15 +02:00
Paolo Bonzini
5d9ec1f4c7 kvm: assume that many ioeventfds can be created
NR_IOBUS_DEVS was increased to 200 in Linux 2.6.34.  By Linux 3.5 it had
increased to 1000 and later ioeventfds were changed to not count against
the limit.  But the earlier limit of 200 would already be enough for
kvm_check_many_ioeventfds() to be true, so remove the check.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25 17:35:15 +02:00