Commit Graph

36898 Commits

Author SHA1 Message Date
Amit Tomar
82e345f57e PPC: e500: Fix GPIO controller interrupt number
The GPIO controller lives at IRQ 47, not 43 on real hardware. This is a problem
because IRQ 43 is occupied by the I2C controller which we want to implement
next, so we'd have a conflict on that IRQ number.

Move the GPIO controller to IRQ 47 where it belongs.

Signed-off-by: Amit Singh Tomar <amit.tomar@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:28 +01:00
Tom Musta
f83c2378bb target-ppc: Introduce Privileged TM Noops
Add the supervisory Transactional Memory instructions treclaim. and
trechkpt.  The implementation is a degenerate one that simply
checks privileged state, TM availability and then sets CR[0] to
0b0000, just like the unprivileged noops.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:28 +01:00
Tom Musta
aeedd58234 target-ppc: Introduce tcheck
Add a degenerate implementation of the Transaction Check (tcheck)
instruction.  Since transaction always immediately fail, this
implementation simply sets CR[BF] to 0b1000, i.e. TDOOMED = 1
and MSR[TS] == 0.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:28 +01:00
Tom Musta
56a846157e target-ppc: Introduce TM Noops
Add degenerate implementations of the non-privileged Transactional
Memory instructions tend., tabort*. and tsr.  This implementation
simply checks the MSR[TM] bit and then sets CR0 to 0b0000.  This
is a reasonable degenerate implementation since transactions are
never allowed to begin and hence MSR[TS] is always 0b00.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:27 +01:00
Tom Musta
0ff93d11bc target-ppc: Introduce tbegin
Provide a degenerate implementation of the tbegin instruction.  This
implementation always fails the transaction, recording the failure
per Book II Section 5.3.2 of the Power ISA V2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:27 +01:00
Tom Musta
aac862379c target-ppc: Introduce TEXASRU Bit Fields
Define mnemonics for the various bit fields in the Transaction
EXception And Summary Register (TEXASR).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:27 +01:00
Tom Musta
3e28c5e363 target-ppc: Power8 Supports Transactional Memory
The Power8 processor implements the Transactional Memory Facility
as defined in Power ISA 2.07.  Update the initialization code to
indicate this.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:27 +01:00
Tom Musta
69d1a93774 target-ppc: Introduce tm_enabled Bit to CPU State
Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit.
This is analogous to the other "available" bits in the MSR (FP,
VSX, etc.).

NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped
with a PPC64 bit check.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:27 +01:00
Tom Musta
e43668a7d2 target-ppc: Introduce Feature Flag for Transactional Memory
Add a flag (POWERPC_FLAG_TM) for the Transactional Memory
Facility introduced in Power ISA 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:27 +01:00
Tom Musta
f90468b646 target-ppc: Introduce Instruction Type for Transactional Memory
Add a category (PPC2_TM) for the Transactional Memory instructions
introduced in Power ISA 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:27 +01:00
Alexey Kardashevskiy
549cfe5d5d pseries: Update SLOF firmware image to 20141202
The changelog is:
  > version: update to 20141202
  > ipv4: Fix send packet across a subnet
  > pci: scan only type 0 and type 1
  > usb-xhci: support xhci extended capabilities
  > Fix term-io-key to also work when stdin has not been set yet
  > net-snk: llfw startup is using the wrong offset to handler
  > net-snk: Make call_client_interface() a bit more ABI compliant
  > net-snk: Remove custom printf version
  > net-snk: Sanitize our .lds file
  > net-snk: Avoid type clash for stdin & stdout
  > net-snk: use socket descriptor in the network stack
  > net-snk: Remove printk() in favor of printf()
  > net-snk: Remove redundant prototypes
  > net-snk: Remove unused timer functions
  > net-snk: Remove some unused PCI functions
  > net-snk: Remove module system
  > net-snk: Remove insmod/rmmod
  > net-snk: Remove snk_kernel_interface and related definitions
  > net-snk: Remove pci/vio_config gunk
  > js2x: Fix build
  > net-snk: Remoe some now unused "kernel" functions
  > rtas: Improve error handling in instantiate-rtas
  > version: update to 20140827
  > Add private HCALL to inform updated RTAS base and entry
  > xhci: fix port assignment

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:27 +01:00
David Gibson
5f9490de56 PPC: Fix crash on spapr_tce_table_finalize()
spapr_tce_table_finalize() can SEGV if the object was not previously
realized.  In particular this can be triggered by running
         qemu-system-ppc -device spapr-tce-table,?

The basic problem is that we have mismatched initialization versus
finalization: spapr_tce_table_finalize() is attempting to undo things that
are done in spapr_tce_table_realize(), not an instance_init function.

Therefore, replace spapr_tce_table_finalize() with
spapr_tce_table_unrealize().

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-stable@nongnu.org
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:26 +01:00
Paolo Bonzini
77bad151fb ppc: do not use get_clock_realtime()
Use the external qemu-timer API instead.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:26 +01:00
Sergey Fedorov
2bf9febc95 device-tree: fix memory leak
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:26 +01:00
Samuel Mendoza-Jonas
e6b8fd246c spapr: Fix stale HTAB during live migration (TCG)
If a TCG guest reboots during a running migration HTAB entries are not
marked dirty, and the destination boots with an invalid HTAB.

When a reboot occurs, explicitly mark the current HTAB dirty after
clearing it.

Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:26 +01:00
Samuel Mendoza-Jonas
338c25b692 spapr: Fix integer overflow during migration (TCG)
The n_valid and n_invalid fields are unsigned short integers but it is
possible to have more than 65535 entries in a contiguous hunk, overflowing
the field. This results in an incorrect HTAB being sent to the destination
during migration.

Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:26 +01:00
Samuel Mendoza-Jonas
01a579729b spapr: Fix stale HTAB during live migration (KVM)
If a guest reboots during a running migration, changes to the
hash page table are not necessarily updated on the destination.
Opening a new file descriptor to the HTAB forces the migration
handler to resend the entire table.

Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:26 +01:00
Cédric Le Goater
e094c4c12f target-ppc: explicitly save page table headers in big endian
Currently, when the page tables are saved, the kvm_get_htab_header structs
and the ptes are assumed being big endian and dumped as a indistinct blob
in the statefile. This is no longer true when the host is little endian
and this breaks restoration.

This patch unfolds the kvmppc_save_htab routine to write explicitly the
kvm_get_htab_header structs in big endian. The ptes are left untouched.

Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:26 +01:00
Tom Musta
58dd0a4787 target-ppc: Eliminate set_fprf Argument From helper_compute_fprf
The set_fprf argument to the helper_compute_fprf helper function
is no longer necessary -- the helper is only invoked when FPSCR[FPRF]
is going to be set.

Eliminate the unnecessary argument from the function signature and
its corresponding implementation.  Change the return value of the
helper to "void".  Update the name of the local variable "ret" to
"fprf", which now makes more sense.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:25 +01:00
Tom Musta
7d45556eff target-ppc: Eliminate set_fprf Argument From gen_compute_fprf
The set_fprf argument to the gen_compute_fprf() utility is no longer
needed -- gen_compute_fprf() is now called only when FPRF is actually
computed and set.  Eliminate the obsolete argument.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:25 +01:00
Tom Musta
00e6fd3e03 target-ppc: Fully Migrate to gen_set_cr1_from_fpscr
Eliminate the set_rc argument from the gen_compute_fprf utility and
the corresponding (and incorrect) implementation.  Replace it with
calls to the gen_set_cr1_from_fpscr() utility.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:25 +01:00
Tom Musta
14ba79c73a target-ppc: mffs. Should Set CR1 from FPSCR Bits
Update the Move From FPSCR (mffs.) instruction to correctly
set CR[1] from FPSCR[FX,FEX,VX,OX].

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:25 +01:00
Tom Musta
4814f2d116 target-ppc: Fix Floating Point Move Instructions That Set CR1
The Floating Point Move instructions (fmr., fabs., fnabs., fneg.,
and fcpsgn.) incorrectly copy FPSCR[FPCC] instead of [FX,FEX,VX,OX].
Furthermore, the current code does this via a call to gen_compute_fprf,
which is awkward since these instructions do not actually set FPRF.

Change the code to use the gen_set_cr1_from_fpscr utility.

Signed-off-by: Tom Musta <tommusta@gmail.com>
[agraf: whitespace fixes]
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:25 +01:00
Tom Musta
b748863a7f target-ppc: VXSQRT Should Not Be Set for NaNs
The Power ISA square root instructions (fsqrt[s], frsqrte[s]) must
set the FPSCR[VXSQRT] flag when operating on a negative value.
However, NaNs have no sign and therefore this flag should not
be set when operating on one.

Change the order of the checks in the helper code.  Move the
SNaN-to-QNaN macro to the top of the file so that it can be
re-used.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:25 +01:00
Tom Musta
2791128e2f target-ppc: Load/Store Vector Element Storage Alignment
The Load Vector Element Indexed and Store Vector Element Indexed
instructions compute an effective address in the usual manner.
However, they truncate that address to the natural boundary.
For example, the lvewx instruction will ignore the least significant
two bits of the address and thus load the aligned word of storage.

Fix the generators for these instruction to properly perform this
truncation.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:25 +01:00
Alexander Graf
cb3778a045 PPC: e500 pci host: Add support for ATMUs
The e500 PCI controller has configurable windows that allow a guest OS
to selectively map parts of the PCI bus space to CPU address space and
to selectively map parts of the CPU address space for DMA requests into
PCI visible address ranges.

So far, we've simply assumed that this mapping is 1:1 and ignored it.

However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live
inside the first 32bits of address space. This means if we always treat
all mappings as 1:1, this map will collide with our RAM map from the CPU's
point of view.

So this patch adds proper ATMU support which allows us to keep the PCICSRBAR
below 32bits local to the PCI bus and have another, different window to PCI
BARs at the upper end of address space. We leverage this on e500plat though,
mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU.

With this patch, I can run guests with lots of RAM and not coincidently access
MSI-X mappings while I really want to access RAM.

Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:24 +01:00
Alexander Graf
44045ce974 PPC: mpc8554ds: Tell user about exceeding RAM limits
The mpc8544ds board only supports up to 3GB of RAM due to its limited
address space.

When the user requests more, abort and tell him that he should use less.

Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:24 +01:00
Alexander Graf
e6b4e5f479 PPC: e500: Move CCSR and MMIO space to upper end of address space
On e500 we're basically guaranteed to have 36bits of physical address space
available for our enjoyment. Older chips (like the mpc8544) only had 32bits,
but everything from e500v2 onwards bumped it up.

It's reasonably safe to assume that if you're using the PV machine, your guest
kernel is configured to support 36bit physical address space. So in order to
support more guest RAM, we can move CCSR and other MMIO windows right below the
end of our 36bit address space, just like later SoC versions of e500 do.

With this patch, I'm able to successfully spawn an e500 VM with -m 48G.

Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:24 +01:00
Alexander Graf
2eaaac1f01 PPC: e500: Move CCSR definition to params
We want to have different MMIO region offsets for the mpc8544ds machine
and our e500 PV machine, so move the definitions of those into the machine
specific params struct.

Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07 16:16:24 +01:00
Paul Moore
ea259acae5 seccomp: add mbind() to the syscall whitelist
The "memory-backend-ram" QOM object utilizes the mbind(2) syscall to
set the policy for a memory range.  Add the syscall to the seccomp
sandbox whitelist.

Signed-off-by: Paul Moore <pmoore@redhat.com>
Signed-off-by: Eduardo Otubo <eduardo.otubo@profitbricks.com>
Acked-by: Eduardo Otubo <eduardo.otubo@profitbricks.com>
Tested-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
2015-01-05 18:13:38 +01:00
Eduardo Otubo
aa49668cc3 seccomp: typo in configure error message
Error message was misleading people to install wrong version of
libseccomp.

Signed-off-by: Eduardo Otubo <eduardo.otubo@profitbricks.com>
2015-01-05 18:08:27 +01:00
Amit Shah
a3a292c420 virtio-rng: fix check for period_ms validity
This was reported for this warning:

hw/virtio/virtio-rng.c:150:31: warning: logical not is only applied to
the left hand side of comparison [-Wlogical-not-parentheses]

Reported-by: dcb
Suggested-by: dcb
Bug: https://bugs.launchpad.net/qemu/+bug/1393486
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Reviewed-by: Amos Kong <akong@redhat.com>
Signed-off-by: Amit Shah <amit.shah@redhat.com>
2015-01-05 14:02:47 +05:30
David Gibson
08f432aa3e virtio-serial: Don't keep a persistent copy of config space
The 'config' field in the VirtIOSerial structure keeps a copy of the virtio
console's config space as visible to the guest, that is to say, in guest
endianness.  This is fiddly to maintain, because on some targets, such as
powerpc, the "guest endianness" can change when a new guest OS boots.

In fact, there's no need to maintain such a guest view of config space -
instead we can reconstruct it from host-format data when it is accessed
with get_config.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Amit Shah <amit.shah@redhat.com>
2015-01-05 12:50:27 +05:30
David Gibson
f2f6e00b2e virtio_serial: Don't use vser->config.max_nr_ports internally
A number of places in the virtio_serial driver retrieve the number of ports
from vser->config.max_nr_ports, which is guest-endian.  But for internal
users, we already have a host-endian copy of the number of ports in
vser->serial.max_virtserial_ports.  Using that instead of the config field
removes the need for easy-to-forget byteswapping.

In particular this fixes a bug on incoming migration, where we don't adjust
the endianness vser->config correctly, because it hasn't yet been loaded
from the migration stream when virtio_serial_load_device() is called.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Amit Shah <amit.shah@redhat.com>
2015-01-05 12:49:58 +05:30
Scott Feldman
5aa8136020 pci: move REDHAT_SDHCI device ID to make room for Rocker
The rocker device uses same PCI device ID as sdhci.  Since rocker device driver
has already been accepted into Linux 3.18, and REDHAT_SDHCI device ID isn't
used by any drivers, it's safe to move REDHAT_SDHCI device ID, avoiding
conflict with rocker.

Signed-off-by: Scott Feldman <sfeldma@gmail.com>
Signed-off-by: Jiri Pirko <jiri@resnulli.us>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-03 09:22:13 +01:00
Peter Wu
debfb917a4 block/iscsi: fix uninitialized variable
'ret' was never initialized in the success path.

Signed-off-by: Peter Wu <peter@lekensteyn.nl>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-03 09:22:13 +01:00
Paolo Bonzini
d13c040409 pckbd: set bits 2-3-6-7 of the output port by default
OSes typically write 0xdd/0xdf to turn the A20 line off and on.  This
has bits 2-3-6-7 on, so that the output port subsection is migrated.
Change the reset value and migration default to include those four
bits, thus avoiding that the subsection is migrated.

This strictly speaking changes guest ABI, but the long time during which
we have not migrated the value means that the guests really do not care
much; so the change is for all machine types.

Reported-by: Igor Mammedov <imammedo@redhat.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-03 09:22:13 +01:00
Paolo Bonzini
bfa7362889 serial: refine serial_thr_ipending_needed
If the THR interrupt is disabled, there is no need to migrate thr_ipending
because LSR.THRE will be sampled again when the interrupt is enabled.
(This is the behavior that is not documented in the datasheet, but
relied on by Windows!)

Note that in this case IIR will never be 0x2 so, if thr_ipending were
to be one, QEMU would produce the subsection.

Reported-by: Igor Mammedov <imammedo@redhat.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-03 09:22:12 +01:00
Paolo Bonzini
cd42d5b236 gen-icount: check cflags instead of use_icount global
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-03 09:22:12 +01:00
Paolo Bonzini
bd79255d25 translate: check cflags instead of use_icount global
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-03 09:22:10 +01:00
Michael Walle
4eab7a0a23 MAINTAINERS: add myself to lm32 and milkymist
Add myself to lm32 and milkymist files.

Signed-off-by: Michael Walle <michael@walle.cc>
2014-12-29 17:25:17 +01:00
Michael Walle
857cccac0d milkymist: softmmu: fix event handling
Keys which send more than one scancode (esp. windows key) weren't handled
correctly since commit 1ff5eedd. Two events were put into the input event
queue but only one was processed. This fixes this by fetching all pending
events in the callback handler.

Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Gerd Hoffmann <kraxel@redhat.com>
2014-12-29 17:24:38 +01:00
Peter Maydell
ab0302ee76 target-arm queue:
* enable 32-bit EL3 (TrustZone) for vexpress and virt boards
  * add fw_cfg device to virt board for UEFI firmware config
  * support passing commandline kernel/initrd to firmware
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJUmXMpAAoJEDwlJe0UNgzeIlIP/24UPoFsA/8rZV9JI41FDGJT
 ZH9SU6mjMhCIYZScbIwr2lfggRMOIzxFe3ohz4pTklXdwwz87Rg8Nfxecg+te/1i
 sqCmhAhsEcZr+Snirn/HmsqPE1dOGoNcCUP4Pb0XByBo3KQ1Gdqj9dUsV2S4CO0M
 ZkxjFaNJrqhyh5PJxoWYqO8aed38v2S+sNA5brCtWsrePo71e89M6qd3JyhKpNWC
 II33HWCS1leBmNc//bWP3DiIiZ1FIwyWgiEhscLD67LhtaQX1Am/x6RAsWzH4T8k
 rH4qZtIIYJi7up1qPCQqUA0TS3TvZuvvY46suAihxgaiLe1p/0KGEvwYmyyg35Pl
 yxdVny21gJi0s/HXVgBGTndjzCBVMfvDoN8BYGRZvuBia1a6QNdRybpiqq/X/8J2
 fPXPgJNuDMzERSrnVHYPqriQpAyNw25gRJqDbo/3xoNS60Yzd4q06yhKxRg8ng3A
 jNrU0O+RVr4IslBXACFPS638WU1n+r6wfN4J/BJvdVugWrIxQ6mSp6ZKdr8dEOMM
 6+R8bVHvCsMdaPB8Hfc94NyagrPM5+JItujfIvE+zRzjdB831IYHVoDOx4MsO+tD
 8A7856tM4/l7LGVbx4ecmLxYyeQyPtEheLkcsaRLJ7FFbt31tnVSCDFcrpzw8TdX
 eRmZTKIFuN1NiaLZ7dev
 =MhXg
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20141223' into staging

target-arm queue:
 * enable 32-bit EL3 (TrustZone) for vexpress and virt boards
 * add fw_cfg device to virt board for UEFI firmware config
 * support passing commandline kernel/initrd to firmware

# gpg: Signature made Tue 23 Dec 2014 13:50:33 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20141223: (31 commits)
  hw/arm/virt: enable passing of EFI-stubbed kernel to guest UEFI firmware
  hw/arm: pass pristine kernel image to guest firmware over fw_cfg
  hw/loader: split out load_image_gzipped_buffer()
  arm: add fw_cfg to "virt" board
  fw_cfg_mem: expose the "data_width" property with fw_cfg_init_mem_wide()
  fw_cfg_mem: introduce the "data_width" property
  exec: allows 8-byte accesses in subpage_ops
  fw_cfg_mem: flip ctl_mem_ops and data_mem_ops to DEVICE_BIG_ENDIAN
  fw_cfg_mem: max access size and region size are the same for data register
  fw_cfg: move boards to fw_cfg_init_io() / fw_cfg_init_mem()
  fw_cfg: hard separation between the MMIO and I/O port mappings
  target-arm: add cpu feature EL3 to CPUs with Security Extensions
  target-arm: Disable EL3 on unsupported machines
  target-arm: Breakout integratorcp and versatilepb cpu init
  target-arm: Set CPU has_el3 prop during virt init
  target-arm: Enable CPU has_el3 prop during VE init
  target-arm: Add arm_boot_info secure_boot control
  target-arm: Add ARMCPU secure property
  target-arm: Add feature unset function
  target-arm: Add virt machine secure property
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-23 15:05:22 +00:00
Peter Maydell
03de06dde5 VFIO updates:
- Conversion to tracepoints (Eric Auger)
 - Fix memory listener address space (Frank Blaschka)
 - Move to hw/vfio/ and split common vs pci (Eric Auger & Kim Phillips)
 - Trivial error_report() fixes (Alex Williamson)
 
 In addition to enabling S390 with the address space fix and updating
 to use tracepoints rather than compile time debug, this set of patches
 moves hw/misc/vfio.c to hw/vfio/ and paves the way for vfio-platform
 support by splitting common functionality from PCI specific code.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUmHzfAAoJECObm247sIsiZwwP/1vaePjmppn2iQkaS/eKssYc
 aHNlQ+zteML0/MMGUsp2d76HinZTStGRAm0yHGQ46Z2XQ+4DT9iARzkferhJKfb9
 jPblAg/ek08WqPvv3epXU81qj/sp0n9MjCz7PJPzSXpKngOaBS5vZp4HJt37+2Kk
 4I3TzKGEaEoAk84Ba8AKp3xG3TcOdnIsg5Ht2cT20QmrGh0R8tXreGavC+ERpJ5/
 59yIewpxxVNDYttD4bqRwyVPup1rpw/qK824cYFz3PWeFzix4rYg8aujr5BxqC5S
 BL6WxHbNC75e8vNZ/toEZX41Dj3jRtXVP3ARCbU0h/5oboUZ+j94eVmRejeCkIor
 G0uJjOT0NTILeq5ZrhGVl7/4reSFyO4EvhF6RDm/913iYJ9xwR1usHyTT3VbUwMh
 3xnCHbGskxVrtdOLHd80o6uEycr4goQip8HP6Xg5YLWauoXHi5oAaOSIeyoHR7JH
 CjnkdmgpSbqBijL+sgAHoRh4hh7hS1sXR4kqeXEdwqZj8be/5v3gb7R/yLlQZYvs
 zAcE16a7CkTvki0f9uKsU2ZGhDE4AQaofB3EnKGSHvmMtGw6PoEDlZFcxtEjbfkl
 RUW6FLxXDVp16wTQCckyT9XPAjsqSFXdiqOf25StR9iwiHDB29hK5JNzM9vTUv06
 AiNWMlxwEYuHu09FKSYi
 =CRNj
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20141222.0' into staging

VFIO updates:
- Conversion to tracepoints (Eric Auger)
- Fix memory listener address space (Frank Blaschka)
- Move to hw/vfio/ and split common vs pci (Eric Auger & Kim Phillips)
- Trivial error_report() fixes (Alex Williamson)

In addition to enabling S390 with the address space fix and updating
to use tracepoints rather than compile time debug, this set of patches
moves hw/misc/vfio.c to hw/vfio/ and paves the way for vfio-platform
support by splitting common functionality from PCI specific code.

# gpg: Signature made Mon 22 Dec 2014 20:19:43 GMT using RSA key ID 3BB08B22
# gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>"
# gpg:                 aka "Alex Williamson <alex@shazbot.org>"
# gpg:                 aka "Alex Williamson <alwillia@redhat.com>"
# gpg:                 aka "Alex Williamson <alex.l.williamson@gmail.com>"

* remotes/awilliam/tags/vfio-update-20141222.0:
  vfio: Cleanup error_report()s
  hw/vfio: create common module
  hw/vfio/pci: use name field in format strings
  hw/vfio/pci: rename group_list into vfio_group_list
  hw/vfio/pci: split vfio_get_device
  hw/vfio/pci: Introduce VFIORegion
  hw/vfio/pci: handle reset at VFIODevice
  hw/vfio/pci: add type, name and group fields in VFIODevice
  hw/vfio/pci: introduce minimalist VFIODevice with fd
  hw/vfio/pci: generalize mask/unmask to any IRQ index
  hw/vfio/pci: Rename VFIODevice into VFIOPCIDevice
  vfio: move hw/misc/vfio.c to hw/vfio/pci.c Move vfio.h into include/hw/vfio
  vfio: fix adding memory listener to the right address space
  vfio: migration to trace points

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-23 14:01:14 +00:00
Paolo Bonzini
0266359e57 cpu-exec: add a new CF_USE_ICOUNT cflag
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-12-23 10:14:53 +01:00
Paolo Bonzini
69b058c881 target-ppc: pass DisasContext to SPR generator functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-12-23 10:14:52 +01:00
Paolo Bonzini
2cbcfb281a atomic: fix position of volatile qualifier
What needs to be volatile is not the pointer, but the pointed-to
value!

Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-12-23 10:14:46 +01:00
Laszlo Ersek
aa351061db hw/arm/virt: enable passing of EFI-stubbed kernel to guest UEFI firmware
The virt board already ensures mutual exclusion between -bios and -pflash
unit#0; we only need to set "bootinfo.firmware_loaded", introduced in the
previous patch, if either of those options was used to load the guest
firmware.

Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-12-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 23:39:20 +00:00
Laszlo Ersek
07abe45c48 hw/arm: pass pristine kernel image to guest firmware over fw_cfg
Introduce the new boolean field "arm_boot_info.firmware_loaded". When this
field is set, it means that the portion of guest DRAM that the VCPU
normally starts to execute, or the pflash chip that the VCPU normally
starts to execute, has been populated by board-specific code with
full-fledged guest firmware code, before the board calls
arm_load_kernel().

Simultaneously, "arm_boot_info.firmware_loaded" guarantees that the board
code has set up the global firmware config instance, for arm_load_kernel()
to find with fw_cfg_find().

Guest kernel (-kernel) and guest firmware (-bios, -pflash) has always been
possible to specify independently on the command line. The following cases
should be considered:

nr  -bios    -pflash  -kernel  description
             unit#0
--  -------  -------  -------  -------------------------------------------
1   present  present  absent   Board code rejects this case, -bios and
    present  present  present  -pflash unit#0 are exclusive. Left intact
                               by this patch.

2   absent   absent   present  Traditional kernel loading, with qemu's
                               minimal board firmware. Left intact by this
                               patch.

3   absent   present  absent   Preexistent case for booting guest firmware
    present  absent   absent   loaded with -bios or -pflash. Left intact
                               by this patch.

4   absent   absent   absent   Preexistent case for not loading any
                               firmware or kernel up-front. Left intact by
                               this patch.

5   present  absent   present  New case introduced by this patch: kernel
    absent   present  present  image is passed to externally loaded
                               firmware in unmodified form, using fw_cfg.

An easy way to see that this patch doesn't interfere with existing cases
is to realize that "info->firmware_loaded" is constant zero at this point.
Which makes the "outer" condition unchanged, and the "inner" condition
(with the fw_cfg-related code) dead.

Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-11-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 23:39:20 +00:00
Laszlo Ersek
7d48a0f721 hw/loader: split out load_image_gzipped_buffer()
In the next patch we'd like to reuse the image decompression facility
without installing the output as a ROM at a specific guest-phys address.

In addition, expose LOAD_IMAGE_MAX_GUNZIP_BYTES, because that's a
straightforward "max_sz" argument for the new load_image_gzipped_buffer().

Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-10-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 23:39:19 +00:00