Commit Graph

85650 Commits

Author SHA1 Message Date
Peter Maydell
6500ac13ff hw/display/pxa2xx: Inline template header
The template header is now included only once; just inline its contents
in hw/display/pxa2xx_lcd.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-10-peter.maydell@linaro.org
2021-03-14 13:14:56 +00:00
Peter Maydell
540817e22f hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
We're about to move code from the template header into pxa2xx_lcd.c.
Before doing that, make coding style fixes so checkpatch doesn't
complain about the patch which moves the code. This commit is
whitespace changes only:
 * avoid hard-coded tabs
 * fix ident on function prototypes
 * no newline before open brace on array definitions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-9-peter.maydell@linaro.org
2021-03-14 13:14:56 +00:00
Peter Maydell
9347e04208 hw/display/pxa2xx: Apply brace-related coding style fixes to template header
We're about to move code from the template header into pxa2xx_lcd.c.
Before doing that, make coding style fixes so checkpatch doesn't
complain about the patch which moves the code. This commit fixes
missing braces in the SKIP_PIXEL() macro definition and in if()
statements.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-8-peter.maydell@linaro.org
2021-03-14 13:14:56 +00:00
Peter Maydell
b48b884fc4 hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
Now that BITS is always 32, expand out all its uses in the template
header, including removing now-useless uses of the glue() macro.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-7-peter.maydell@linaro.org
2021-03-14 13:14:55 +00:00
Peter Maydell
9e53ecdc20 hw/display/pxa2xx_lcd: Remove dest_width state field
Since the dest_width is now always 4 because the output surface is
32bpp, we can replace the dest_width state field with a constant.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-6-peter.maydell@linaro.org
2021-03-14 13:14:55 +00:00
Peter Maydell
e834dfc64c hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel.  Remove the legacy dead code
from the pxa2xx_lcd display device which was handling the possibility
that the console surface was some other format.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-5-peter.maydell@linaro.org
2021-03-14 13:14:55 +00:00
Peter Maydell
ba1c16e425 hw/display/pl110: Remove use of BITS from pl110_template.h
BITS is always 32, so remove all uses of it from the template header,
by dropping the trailing '32' from the draw function names and
not constructing the name of rgb_to_pixel32() via the glue() macro.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-4-peter.maydell@linaro.org
2021-03-14 13:14:55 +00:00
Peter Maydell
560ebce6b2 hw/display/pl110: Pull included-once parts of template header into pl110.c
The pl110_template.h header has a doubly-nested multiple-include pattern:
 * pl110.c includes it once for each host bit depth (now always 32)
 * every time it is included, it includes itself 6 times, to account
   for multiple guest device pixel and byte orders

Now we only have to deal with 32-bit host bit depths, we can move the
code corresponding to the outer layer of this double-nesting to be
directly in pl110.c and reduce the template header to a single layer
of nesting.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-3-peter.maydell@linaro.org
2021-03-14 13:14:55 +00:00
Peter Maydell
62bdc8c164 hw/display/pl110: Remove dead code for non-32-bpp surfaces
For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel. Remove the legacy dead
code from the pl110 display device which was handling the
possibility that the console surface was some other format.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-2-peter.maydell@linaro.org
2021-03-14 13:14:55 +00:00
Philippe Mathieu-Daudé
d27fadddc6 target/mips/tx79: Salvage instructions description comment
This comment describing the tx79 opcodes is helpful. As we
will implement these instructions in tx79_translate.c, move
the comment there.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-15-f4bug@amsat.org>
2021-03-13 23:43:30 +01:00
Philippe Mathieu-Daudé
e71d0f56ce target/mips: Remove 'C790 Multimedia Instructions' dead code
We have almost 400 lines of code full of /* TODO */ comments
which end calling gen_reserved_instruction().

As we are not going to implement them, and all the caller's
switch() default cases already call gen_reserved_instruction(),
we can remove this altogether.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-14-f4bug@amsat.org>
2021-03-13 23:43:27 +01:00
Philippe Mathieu-Daudé
94c882f7d1 target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
2021-03-13 23:43:24 +01:00
Philippe Mathieu-Daudé
5a976c0025 target/mips/tx79: Move PCPYH opcode to decodetree
Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree.
Remove unnecessary code / comments.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
2021-03-13 23:43:20 +01:00
Philippe Mathieu-Daudé
ca8def9bdb target/mips/translate: Simplify PCPYH using deposit_i64()
Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-11-f4bug@amsat.org>
2021-03-13 23:43:17 +01:00
Philippe Mathieu-Daudé
f9fa53f197 target/mips/translate: Make gen_rdhwr() public
We will use gen_rdhwr() outside of translate.c, make it public.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-28-f4bug@amsat.org>
2021-03-13 23:43:14 +01:00
Philippe Mathieu-Daudé
1f9408d550 target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
2021-03-13 23:43:11 +01:00
Philippe Mathieu-Daudé
ffc672aa97 target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.

As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-03-13 23:43:07 +01:00
Philippe Mathieu-Daudé
c27b457937 target/mips: Use gen_load_gpr[_hi]() when possible
Use gen_load_gpr[_hi]() instead of open coding it.

Patch generated using the following spatch script:

  @gen_load_gpr@
  identifier reg_idx;
  expression tcg_reg;
  @@
  -if (reg_idx == 0) {
  -    tcg_gen_movi_tl(tcg_reg, 0);
  -} else {
  -    tcg_gen_mov_tl(tcg_reg, cpu_gpr[reg_idx]);
  -}
  +gen_load_gpr(tcg_reg, reg_idx);

  @gen_load_gpr_hi@
  identifier reg_idx;
  expression tcg_reg;
  @@
  -if (reg_idx == 0) {
  -    tcg_gen_movi_i64(tcg_reg, 0);
  -} else {
  -    tcg_gen_mov_i64(tcg_reg, cpu_gpr_hi[reg_idx]);
  -}
  +gen_load_gpr_hi(tcg_reg, reg_idx);

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210308131604.460693-1-f4bug@amsat.org>
2021-03-13 23:43:04 +01:00
Philippe Mathieu-Daudé
b24db6fcd4 target/mips: Extract MXU code to new mxu_translate.c file
Extract 1600+ lines from the big translate.c into a new file.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-14-f4bug@amsat.org>
2021-03-13 23:43:02 +01:00
Philippe Mathieu-Daudé
fe35ea9483 target/mips: Introduce mxu_translate_init() helper
Extract the MXU register initialization code from mips_tcg_init()
as a new mxu_translate_init() helper. Make it public and replace
!TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to
elide this code at preprocessing time.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-13-f4bug@amsat.org>
2021-03-13 23:43:00 +01:00
Philippe Mathieu-Daudé
c7abe00ae9 target/mips: Simplify decode_opc_mxu() ifdef'ry
By making the prototype public and checking
'TARGET_LONG_BITS == 32' we let the compiler
elide the decode_opc_mxu() call.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-12-f4bug@amsat.org>
2021-03-13 23:42:58 +01:00
Philippe Mathieu-Daudé
a8dad35388 target/mips: Convert decode_ase_mxu() to decodetree prototype
To easily convert MXU code to decodetree, making it return a boolean.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-11-f4bug@amsat.org>
2021-03-13 23:42:56 +01:00
Philippe Mathieu-Daudé
e31b43ec50 target/mips: Rename decode_opc_mxu() as decode_ase_mxu()
Use "decode_{isa,ase,ext}_$name()" function name pattern for
public decodetree entrypoints.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-10-f4bug@amsat.org>
2021-03-13 23:42:55 +01:00
Philippe Mathieu-Daudé
2234528618 target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()
Move the check for MUL opcode from decode_opc_mxu() callee
to decode_opc_legacy() caller, so we can simplify the ifdef'ry
and elide the call in few commits.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-9-f4bug@amsat.org>
2021-03-13 23:42:53 +01:00
Philippe Mathieu-Daudé
de5af7c5e6 target/mips: Use OPC_MUL instead of OPC__MXU_MUL
We already have a macro and definition to extract / check
the Special2 MUL opcode. Use it instead of the unnecessary
OPC__MXU_MUL macro.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-8-f4bug@amsat.org>
2021-03-13 23:42:52 +01:00
Philippe Mathieu-Daudé
965eb74bb5 target/mips: Pass instruction opcode to decode_opc_mxu()
In the next commit we'll make decode_opc_mxu() match decodetree
prototype by returning a boolean. First pass ctx->opcode as an
argument.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-7-f4bug@amsat.org>
2021-03-13 23:42:50 +01:00
Philippe Mathieu-Daudé
21d66ead6a target/mips: Remove unused CPUMIPSState* from MXU functions
None of these MXU functions use their CPUMIPSState* env argument,
remove it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-6-f4bug@amsat.org>
2021-03-13 23:42:49 +01:00
Philippe Mathieu-Daudé
2090713f65 target/mips: Remove XBurst Media eXtension Unit dead code
All these unimplemented MXU opcodes end up calling
gen_reserved_instruction() which is the default switch
case in decode_opc_mxu().

The translate.c file is already big enough and hard to maintain,
remove 1300 lines of unnecessary code and /* TODO */ comments.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-5-f4bug@amsat.org>
2021-03-13 23:42:47 +01:00
Philippe Mathieu-Daudé
4f57f43cb8 target/mips: Rewrite complex ifdef'ry
No need for this obfuscated ifdef'ry, KISS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-4-f4bug@amsat.org>
2021-03-13 23:42:45 +01:00
Philippe Mathieu-Daudé
21fb03be67 target/mips/meson: Restrict mips-semi.c to TCG
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-3-f4bug@amsat.org>
2021-03-13 23:42:43 +01:00
Philippe Mathieu-Daudé
2897579982 target/mips/meson: Introduce mips_tcg source set
Introduce the 'mips_tcg' source set to collect TCG specific files.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-2-f4bug@amsat.org>
2021-03-13 23:42:31 +01:00
Philippe Mathieu-Daudé
f8ead0d7bd hw/mips/gt64xxx: Trace accesses to ISD registers
Trace all accesses to Internal Space Decode (ISD) registers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-6-f4bug@amsat.org>
2021-03-13 20:29:36 +01:00
Philippe Mathieu-Daudé
1b3422bde2 hw/mips/gt64xxx: Rename trace events related to interrupt registers
We want to trace all register accesses. First rename the current
gt64120_read / gt64120_write events with '_intreg' suffix, as they
are restricted to interrupt registers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-5-f4bug@amsat.org>
2021-03-13 20:29:36 +01:00
Philippe Mathieu-Daudé
1c8d4071ee hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats
Fix the following typos:
- GT_PCI1_CFGDATA is not a timer register but a PCI one,
- zero-padding flag is out of the format

Fixes: 641ca2bfcd ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-4-f4bug@amsat.org>
2021-03-13 20:29:36 +01:00
Philippe Mathieu-Daudé
8d492c5f06 hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers
The ISD MemoryRegion is implemented for 32-bit accesses.
Simplify it by setting the MemoryRegionOps::impl min/max
access size fields.

Since the region is registered with a size of 0x1000 bytes,
we can remove the hwaddr mask.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-3-f4bug@amsat.org>
2021-03-13 20:29:36 +01:00
Philippe Mathieu-Daudé
260290677e hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize()
The ISD I/O region belongs to the TYPE_GT64120_PCI_HOST_BRIDGE,
so initialize it before it is realized, not after.
Rename the region as 'gt64120-isd' so it is clearer to realize
it belongs to the GT64120 in the memory tree view.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-2-f4bug@amsat.org>
2021-03-13 20:29:36 +01:00
Vincent Fazio
0266e8e3b3 linux-user/elfload: fix address calculation in fallback scenario
Previously, guest_loaddr was not taken into account when returning an
address from pgb_find_hole when /proc/self/maps was unavailable which
caused an improper guest_base address to be calculated.

This could cause a SIGSEGV later in load_elf_image -> target_mmap for
ET_EXEC type images since the mmap MAP_FIXED flag is specified which
could clobber existing mappings at the address returnd by g2h().

  mmap(0xd87000, 16846912, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_NORESERVE|0x100000, -1, 0) = 0xd87000
  munmap(0xd87000, 16846912)              = 0
  write(2, "Locating guest address space @ 0"..., 40Locating guest address space @ 0xd87000) = 40
  mmap(0x1187000, 16850944, PROT_NONE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS|MAP_NORESERVE, -1, 0) = 0x1187000
  --- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_ACCERR, si_addr=0x2188310} ---
  +++ killed by SIGSEGV +++

Now, pgd_find_hole accounts for guest_loaddr in this scenario.

Fixes: ad592e37df ("linux-user: provide fallback pgd_find_hole for bare chroots")
Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20210131061948.15990-1-vfazio@xes-inc.com>
[lv: updated it to check if ret == -1]
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-13 10:45:11 +01:00
Vincent Fazio
934eed5178 linux-user/elfload: do not assume MAP_FIXED_NOREPLACE kernel support
Previously, pgd_find_hole_fallback assumed that if the build host's libc
had MAP_FIXED_NOREPLACE defined that the address returned by mmap would
match the requested address. This is not a safe assumption for Linux
kernels prior to 4.17

Now, we always compare mmap's resultant address with the requested
address and no longer short-circuit based on MAP_FIXED_NOREPLACE.

Fixes: 2667e069e7 ("linux-user: don't use MAP_FIXED in pgd_find_hole_fallback")
Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210131061930.14554-1-vfazio@xes-inc.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-13 10:45:11 +01:00
Vincent Fazio
7e588fbc57 linux-user/elfload: munmap proper address in pgd_find_hole_fallback
Previously, if the build host's libc did not define MAP_FIXED_NOREPLACE
or if the running kernel didn't support that flag, it was possible for
pgd_find_hole_fallback to munmap an incorrect address which could lead to
SIGSEGV if the range happened to overlap with the mapped address of the
QEMU binary.

  mmap(0x1000, 22261224, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_NORESERVE, -1, 0) = 0x7f889d331000
  munmap(0x1000, 22261224)                = 0
  --- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x84b817} ---
  ++ killed by SIGSEGV +++

Now, always munmap the address returned by mmap.

Fixes: 2667e069e7 ("linux-user: don't use MAP_FIXED in pgd_find_hole_fallback")
Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210131061849.12615-1-vfazio@xes-inc.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-13 10:45:11 +01:00
Laurent Vivier
6e1c0d7b95 linux-user: manage binfmt-misc preserve-arg[0] flag
Add --preserve-argv0 in qemu-binfmt-conf.sh to configure the preserve-argv0
flag.

This patch allows to use new flag in AT_FLAGS to detect if
preserve-argv0 is configured for this interpreter:
argv[0] (the full pathname provided by binfmt-misc) is removed and
replaced by argv[1] (the original argv[0] provided by binfmt-misc when
'P'/preserve-arg[0] is set)

For instance with this patch and kernel support for AT_FLAGS:

  $ sudo chroot m68k-chroot sh -c 'echo $0'
  sh

without this patch:

  $ sudo chroot m68k-chroot sh -c 'echo $0'
  /usr/bin/sh

The new flag is available in kernel (v5.12) since:
2347961b11d4 ("binfmt_misc: pass binfmt_misc flags to the interpreter")

This can be tested with something like:

  # cp ..../qemu-ppc /chroot/powerpc/jessie

  # qemu-binfmt-conf.sh --qemu-path / --systemd ppc --credential yes \
                        --persistent no --preserve-argv0 yes
  # systemctl restart systemd-binfmt.service
  # cat /proc/sys/fs/binfmt_misc/qemu-ppc
  enabled
  interpreter //qemu-ppc
  flags: POC
  offset 0
  magic 7f454c4601020100000000000000000000020014
  mask ffffffffffffff00fffffffffffffffffffeffff
  # chroot /chroot/powerpc/jessie  sh -c 'echo $0'
  sh

  # qemu-binfmt-conf.sh --qemu-path / --systemd ppc --credential yes \
                        --persistent no --preserve-argv0 no
  # systemctl restart systemd-binfmt.service
  # cat /proc/sys/fs/binfmt_misc/qemu-ppc
  enabled
  interpreter //qemu-ppc
  flags: OC
  offset 0
  magic 7f454c4601020100000000000000000000020014
  mask ffffffffffffff00fffffffffffffffffffeffff
  # chroot /chroot/powerpc/jessie  sh -c 'echo $0'
  /bin/sh

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20210222105004.1642234-1-laurent@vivier.eu>
2021-03-13 10:45:11 +01:00
Nicolas Surbayrole
08f3a96b33 linux-user: Fix executable page of /proc/self/maps
The guest binary and libraries are not always map with the
executable bit in the host process. The guest may read a
/proc/self/maps with no executable address range. The
perm fields should be based on the guest permission inside
Qemu.

Signed-off-by: Nicolas Surbayrole <nsurbayrole@quarkslab.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210308091959.986540-1-nsurbayrole@quarkslab.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-13 10:45:11 +01:00
Peter Maydell
8e6bc6cdc8 Prepare MacOS ROM support:
- add RTR instruction
   - fix unaligned access requirement
   - fix ATC bit (68040 MMU)
 -----BEGIN PGP SIGNATURE-----
 
 iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmBKlyMSHGxhdXJlbnRA
 dml2aWVyLmV1AAoJEPMMOL0/L748RNYP/A/5lAz3t91tx65RX12pYCMNzyhtfL+q
 UZeLx2YFJpruKEpcjS3a7/gUP/KoTf24CQOsAE6ETIsSshxBBeM+BF5/TaBlSv5G
 tc68GNNp7fSqPakqUG1WOsMeFjkl+2x52vWGRIef4b/fEHrjuOwPoN7SxTqcBCAa
 f9/A+9E0mTKbuZmKi+cYwk9LM2IadQndvV/M4UVBn6arWSQhkpuXg5t6IGxfAWQG
 C9PAuCWJy/MeCua7gkqWOlB3oBNBI3aVY1JZjvjTh2bUqXuZ2gnpkXpROrmJ5d44
 LFn1zWRuhL9Lpu/Cf6i5a2gnDrc3AE7s4cfOII1VpmVoc8QEfUcPC2IGA2OCG6x/
 MLNr5pRbHn/2pEWt9qsjePBq21AciODGSsz2DQb8hGlDVlFW1b2cD0W5wubxAX9D
 YfRDMTq5CeTCELnuBfd2Wd/Isg+ucmRH9wo0TQ4gxiRw7r1iZbPa/OUcbVeJmFCo
 u4YSHLjzEWHdMsKdAXdc75eSyaHn0DcdCaCWoGCa5CUMIUeqBsO09EeaTBSPMmk4
 azD658vpSiscRaYntXDsFPnKxYYfgFm9JiX0t5TBAeIX7WvXTNY3sws64FBsucEL
 pdM+3w+slwRWT2033Rekt4TZHYzCJYLTs4uCyGtXZVL373whedvS8H29iGXsfSQ0
 pM2r7u/BF7kc
 =Xrpn
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging

Prepare MacOS ROM support:
  - add RTR instruction
  - fix unaligned access requirement
  - fix ATC bit (68040 MMU)

# gpg: Signature made Thu 11 Mar 2021 22:18:11 GMT
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/m68k-for-6.0-pull-request:
  target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature
  target/m68k: reformat m68k_features enum
  target/m68k: don't set SSW ATC bit for physical bus errors
  target/m68k: implement rtr instruction

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-12 18:56:56 +00:00
John Snow
33bf47291e README: Add Documentation blurb
Add it in a prominent place: Right after figuring out what QEMU is,
users may wish to know how to use it more than they want to know how to
build their own version of it.

Signed-off-by: John Snow <jsnow@redhat.com>
Message-Id: <20201104193032.1319248-1-jsnow@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-03-12 15:46:30 +01:00
Thomas Huth
9872ba0a8a MAINTAINERS: Merge the Gitlab-CI section into the generic CI section
The status of the gitlab-CI files is currently somewhat confusing, and
it is often not quite clear whether a patch should go via my tree or
via the testing tree of Alex. That situation has grown historically...
Initially, I was the only one using the gitlab-CI, just for my private
repository there. But in the course of time, the gitlab-CI switched to
use the containers from tests/docker/ (which is not part of the gitlab-CI
section in the MAINTAINERS file), and QEMU now even switched to gitlab.com
completely for the repository and will soon use it as its gating CI, too,
so it makes way more sense if the gitlab-ci.yml files belong to the people
who are owning the qemu-project on gitlab.com and take care of the gitlab
CI there. Thus let's merge the gitlab-ci section into the common "test and
build automation" section.

And while we're at it, I'm also removing the line with Fam there for now,
since he was hardly active during the last years in this area anymore.
If he ever gets more time for this part again in the future, we surely
can add the line back again. I'm also removing the Patchew URL from this
section now since Patchew's files are not tracked in the main QEMU repo
and it is also not maintained by Alex, Philippe and myself.
The maintainers of Patchew are still listed more accurately in the wiki on
https://wiki.qemu.org/AdminContacts & https://wiki.qemu.org/Testing/CI/Patchew
instead.

Now to avoid that Alex is listed here in this section alone, Philippe and
I agreed to help as backup maintainers here, too. And Willian volunteered
to be an additional reviewer.

Message-Id: <20210309112356.737266-1-thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Acked-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Acked-by: Fam Zheng <fam@euphon.net>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-03-12 15:46:30 +01:00
Paolo Bonzini
8e19c0098c tests: remove "make check-speed" in favor of "make bench"
"make check-speed" has been broken since the removal of ninja2make
last October.  It was just a backwards-compatibility alias for
"make bench-speed", which in turn is in principle a subset of
"make bench".  Advertise the latter and drop "make check-speed"
completely since no one has noticed.

Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210310164612.285362-1-pbonzini@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-03-12 15:46:30 +01:00
Thomas Huth
342409564c gitlab-ci.yml: Merge check-crypto-old jobs into the build-crypto-old jobs
Both, the build-crypto-old and the check-crypto-old jobs finish reasonably
fast, and the build artifacts are only used for the single corresponding
check jobs, so there is no reason for doing the check step in a separate
job here. Thus let's stop wasting artifacts space and job scheduler over-
head by simply merging the test step into the build jobs.

Message-Id: <20210311142211.1547864-5-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-03-12 15:46:30 +01:00
Thomas Huth
7da153e818 gitlab-ci.yml: Merge one of the coroutine jobs with the tcg-disabled job
Our gitlab-ci got quite slow in the past weeks, due to the immense amount
of jobs that we have, so we should try to reduce the number of jobs.
Since we already have a job that builds without TCG, we can merge
one of the "build-coroutine" jobs with it to get rid of at least one
job.

Message-Id: <20210311142211.1547864-4-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-03-12 15:46:30 +01:00
Thomas Huth
4a859abd1d gitlab-ci.yml: Add some missing dependencies to the jobs
Let's make sure that all jobs have proper "needs:" statements so that
they can start as soon as possible, without having to wait for the
previous pipeline stage to finish.

Message-Id: <20210311142211.1547864-3-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-03-12 15:46:30 +01:00
Thomas Huth
dd188e4184 gitlab-ci.yml: Move build-tools-and-docs-debian to a better place
The "build-tools-and-docs-debian" job had been added in between
the "check-system-debian" and the "accepance-system-debian" jobs
and thus separates the jobs that belong together. Move it away,
to the end of the file, next to the "pages" job that depends on it.
And while we're at it, also add a proper "needs:" line to the
job so that it can be started as soon as possible instead of always
waiting for the previous stage to finish.

Message-Id: <20210311142211.1547864-2-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-03-12 15:46:30 +01:00
Thomas Huth
3b472e71d5 tests: Move benchmarks into a separate folder
Make it clear that these files are related to benchmarks by moving
them into a new folder called "bench".

Message-Id: <20210312092238.79509-1-thuth@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-03-12 15:46:30 +01:00