Commit Graph

14 Commits

Author SHA1 Message Date
Aurelien Jarno
cf7e0c80aa target-cris: Switch to AREG0 free mode
Add an explicit CPUCRISState parameter instead of relying on AREG0, and
use cpu_ld* in translation and interrupt handling. Remove AREG0 swapping
in tlb_fill(). Switch to AREG0 free mode

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15 17:44:33 +00:00
Aurelien Jarno
febc9920c6 target-cris: Avoid AREG0 for helpers
Add an explicit CPUCRISState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15 17:44:33 +00:00
Edgar E. Iglesias
f756c7a723 cris: Add break support for v10.
Still no retb

Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2012-06-14 15:29:11 +02:00
Andreas Färber
a1170bfd19 target-cris: Don't overuse CPUState
Scripted conversion:
  sed -i "s/CPUState/CPUCRISState/g" target-cris/*.[hc]
  sed -i "s/#define CPUCRISState/#define CPUState/" target-cris/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:25 +01:00
Stefan Sandstrom
774d5c5b16 cris: Handle conditional stores on CRISv10
Signed-off-by: Stefan Sandstrom <Stefan.Sandstrom@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-12-12 11:38:31 +01:00
Edgar E. Iglesias
3ab20e206c cris: Handle opcode zero
It's a valid branch pc + 2.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-06-28 20:52:37 +02:00
Stefan Weil
8186e78311 Fix typo in comment (truely -> truly)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-08 10:02:18 +01:00
Edgar E. Iglesias
5cabc5ccfe cris: Allow more TB chaining for crisv10
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2011-01-10 23:24:36 +01:00
Blue Swirl
03e654c083 cris: avoid a write only variable
Compiling with GCC 4.6.0 20100925 produced a warning:
In file included from /src/qemu/target-cris/translate.c:3154:0:
/src/qemu/target-cris/translate_v10.c: In function 'dec10_prep_move_m':
/src/qemu/target-cris/translate_v10.c:111:22: error: variable 'rd' set but not used [-Werror=unused-but-set-variable]

Fix by deleting rd, adjust the only user.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-13 18:42:35 +00:00
Blue Swirl
43dc2a645e Replace assert(0) with abort() or cpu_abort()
When building with -DNDEBUG, assert(0) will not stop execution
so it must not be used for abnormal termination.

Use cpu_abort() when in CPU context, abort() otherwise.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-18 18:41:57 +00:00
Blue Swirl
70539e1850 Update to a hopefully more future proof FSF address
See also 8167ee8839,
530e7615ce and
fad6cb1a56.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-07 15:48:43 +00:00
Edgar E. Iglesias
4ffb9ae2e1 cris: Mask interrupts on dslots for CRISv10.
CRISv10 cores (unlike v32) do not take any interrupts while delayed
jumps are pending (delay slots).

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-02-20 19:17:29 +01:00
Edgar E. Iglesias
bf76bafa5a crisv10: Prettify.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-02-15 23:39:48 +01:00
Edgar E. Iglesias
40e9eddd38 cris: Add support for CRISv10 translation.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-02-15 12:18:57 +01:00