Commit Graph

569 Commits

Author SHA1 Message Date
Stefan Weil
5ddd17b403 tcg/s390: Only one call output register needed for 64 bit hosts
The second register is only needed for 32 bit hosts.

Cc: Alexander Graf <agraf@suse.de>
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:55:21 +00:00
Stefan Weil
af15a62309 tcg/ia64: Only one call output register needed for 64 bit hosts
The second register is never used for ia64 hosts.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:54:57 +00:00
Stefan Weil
68af23af69 tcg/i386: Only one call output register needed for 64 bit hosts
The second register is only needed for 32 bit hosts.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:54:49 +00:00
Thomas Huth
e89720b116 tcg/ppc64: Fix zero extension code generation bug for ppc64 host
The ppc64 code generation backend uses an rldicr (Rotate Left Double
Immediate and Clear Right) instruction to implement zero extension of
a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64).  However
this is wrong - this instruction clears specified low bits of the
value, instead of high bits as we require for a zero extension.  It
should instead use an rldicl (Rotate Left Double Immediate and Clear
Left) instruction.

Presumably amongst other things, this causes the SLOF firmware image
used with -M pseries to not boot on a ppc64 host.

It appears this bug was exposed by commit
0bf1dbdcc9 (tcg/ppc64: fix 16/32 mixup)
which enabled the use of the op_ext32u_i64 operation on the ppc64
backend.

Signed-off-by: Thomas Huth <thuth@de.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: malc <av1474@comtv.ru>
2011-09-09 19:07:06 +04:00
Peter Maydell
70d705fd46 tcg/ppc/tcg-target.c: Avoid 'set but not used' gcc warnings
Move the declaration and initialisation of some variables in
tcg_out_qemu_ld and tcg_out_qemu_st inside CONFIG_SOFTMMU, to
avoid the "variable set but not used" warning of gcc 4.6.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: malc <av1474@comtv.ru>
2011-09-01 21:20:50 +04:00
Blue Swirl
fe0de7aa5e TCG: improve optimizer debugging
Use enum TCGOpcode instead of plain old int so that the name of
current op can be seen in GDB. Add a default case to switch
so that GCC does not complain about unhandled enum cases.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-28 07:17:27 +00:00
Richard Henderson
f412c762e2 tcg: Update --enable-debug for TCG_OPF_NOT_PRESENT.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-23 21:24:39 +02:00
malc
0bf1dbdcc9 tcg/ppc64: fix 16/32 mixup
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22 18:26:15 +04:00
malc
157f2662fb tcg/ppc64: implement not_i32/64 and ext32u_i64
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22 14:40:00 +04:00
malc
350dba6ce6 tcg/ppc32: implement deposit_i32
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22 14:39:00 +04:00
Richard Henderson
64ba39af27 tcg-ia64: Fix typos in AREG0 setup in prologue.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:26 +00:00
Richard Henderson
6e6a99249c tcg-hppa: Fix CPU_TEMP_BUF_NLONGS oversight.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:25 +00:00
Richard Henderson
cb25c80a9b tcg: Constant fold neg, andc, orc, eqv, nand, nor.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:25 +00:00
Richard Henderson
25c4d9cc84 tcg: Always define all of the TCGOpcode enum members.
By always defining these symbols, we can eliminate a lot of ifdefs.

To allow this to be checked reliably, the semantics of the
TCG_TARGET_HAS_* macros must be changed from def/undef to true/false.
This allows even more ifdefs to be removed, converting them into
C if statements.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:24 +00:00
Richard Henderson
8399ad59e7 tcg: Add and use TCG_OPF_64BIT.
This allows the simplification of the op_bits function from
tcg/optimize.c.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:22 +00:00
Anthony Liguori
7267c0947d Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-20 23:01:08 -05:00
Blue Swirl
e31b0a7c05 TCG: fix copy propagation
Copy propagation introduced in 22613af4a6
considered only global registers. However, register temps and stack
allocated locals must be handled differently because register temps
don't survive across brcond.

Fix by propagating only within same class of temps.

Tested-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-07 09:33:20 +00:00
Blue Swirl
2ec00650f6 TCG: fix breakage by previous patch
Fix incorrect logic and typos in previous commit
1bfd07bdfe.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 18:54:23 +00:00
Blue Swirl
1bfd07bdfe TCG: fix breakage on some RISC hosts
Fix breakage by a640f03178
and 55c0975c5b.

Some TCG targets don't implement all TCG ops, so make
optimizing those conditional.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 12:21:33 +00:00
Kirill Batuzov
a640f03178 Do constant folding for unary operations.
Perform constant folding for NOT and EXT{8,16,32}{S,U} operations.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:30 +00:00
Kirill Batuzov
55c0975c5b Do constant folding for shift operations.
Perform constant forlding for SHR, SHL, SAR, ROTR, ROTL operations.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:29 +00:00
Kirill Batuzov
9a81090b12 Do constant folding for boolean operations.
Perform constant folding for AND, OR, XOR operations.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:29 +00:00
Kirill Batuzov
53108fb574 Do constant folding for basic arithmetic operations.
Perform actual constant folding for ADD, SUB and MUL operations.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:28 +00:00
Kirill Batuzov
22613af4a6 Add copy and constant propagation.
Make tcg_constant_folding do copy and constant propagation. It is a
preparational work before actual constant folding.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:27 +00:00
Kirill Batuzov
8f2e8c07a6 Add TCG optimizations stub
Added file tcg/optimize.c to hold TCG optimizations. Function tcg_optimize
is called from tcg_gen_code_common. It calls other functions performing
specific optimizations. Stub for constant folding was added.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:25 +00:00
Stefan Weil
ea15fb0672 tcg/mips: Fix regression caused by typo (copy + paste bug)
cppcheck reports an error:
qemu/tcg/mips/tcg-target.c:1487: error: Invalid number of character (()

The unpatched code won't compile on mips hosts starting with commit
cea5f9a28f.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 21:03:37 +00:00
Peter Maydell
107a47cc2d tcg/README: Expand advice on number of TCG ops per target insn
Expand the note on the number of TCG ops generated per target insn,
to be clearer about the range of applicability of the 20 op rule
of thumb. Also add a note about the hard MAX_OP_PER_INSTR limit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-16 13:17:36 +00:00
Blue Swirl
f74b32dec9 TCG/PPC: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-02 18:48:28 +00:00
Richard Henderson
ec1884298c tcg-hppa: Support deposit opcode.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01 21:07:28 +00:00
Blue Swirl
2a6a665f16 TCG/HPPA: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01 20:52:40 +00:00
Blue Swirl
a42bceec09 TCG/HPPA: use TCG_REG_CALL_STACK instead of TCG_REG_SP
Use TCG_REG_CALL_STACK instead of TCG_REG_SP for consistency.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01 20:49:51 +00:00
malc
c24a9c6ef9 tcg/ppc64: Remove tcg_out_addi
The only user (within tcg.c) was removed

Signed-off-by: malc <av1474@comtv.ru>
2011-06-28 02:27:52 +04:00
malc
1a2eb16241 tcg/ppc: Remove tcg_out_addi
The only user (within tcg.c) was removed

Signed-off-by: malc <av1474@comtv.ru>
2011-06-28 02:26:06 +04:00
Blue Swirl
f44c99607a TCG/Sparc64: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.

On Sparc64, stack pointer is not aligned but there is a fixed bias of 2047,
so don't try to enforce alignment.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:53 +00:00
Blue Swirl
ac0275dcfe TCG/x86: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG
temps.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:51 +00:00
Blue Swirl
e83c80f718 TCG/x86: use TCG_REG_CALL_STACK instead of TCG_REG_ESP
Except for specific cases where the use of %esp changes the encoding of
the instruction, it's cleaner to use TCG_REG_CALL_STACK instead of
TCG_REG_ESP.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:49 +00:00
Blue Swirl
345649c054 TCG: remove broken stack allocation for call arguments
The code for stack allocation for call arguments is way too simplistic
to actually work on targets with non-trivial stack allocation policies,
e.g. ppc64. We've also already allocated TCG_STATIC_CALL_ARGS_SIZE worth
of stack for calls which should be well more than any helper needs.

Remove broken dynamic stack allocation code and replace it with an assert.
Should dynamic stack allocation ever be needed again, target specific
functions should be added.

Thanks to Richard Henderson for the analysis.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:47 +00:00
Blue Swirl
b591dc59bc TCG: fix negative frame offset calculations
size_t is unsigned, so the frame offset calculations can be incorrect for
negative offsets.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:44 +00:00
Blue Swirl
614f104dfd Delegate setup of TCG temporaries to targets
Delegate TCG temp_buf setup to targets, so that they can use a stack
frame later instead.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:43 +00:00
Blue Swirl
cea5f9a28f cpu-exec.c: avoid AREG0 use
Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.

Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue
change.

Revert the hacks to avoid AREG0 use on Sparc hosts.

Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h.

Compile the file without HELPER_CFLAGS.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:38 +00:00
Blue Swirl
2b41f10e18 Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:35 +00:00
Christophe Fergeau
568fffe353 tcg: Fix unused-but-set-variable warning
Based on a patch from Hans de Goede <hdegoede@redhat.com>

This warning is new in gcc 4.6.

Acked-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Christophe Fergeau <cfergeau@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 18:32:46 +02:00
Peter Maydell
ebecf36381 tcg: If DEBUG_TCGV, distinguish TCGv_ptr from TCGv_i32/TCGv_i64
When compiling with DEBUG_TCGV enabled, make the TCGv_ptr type distinct
from TCGv_i32/TCGv_i64. This means that using an i32 or i64 TCG op to
manipulate a TCGv_ptr will always be detected at compile time, rather
than only if compiling on a host system with the other word size.

NB: the tcg_add_ptr and tcg_sub_ptr macros have been removed as they
were not used anywhere.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 18:26:21 +02:00
Peter Maydell
6bd4b08ab2 tcg/tcg-op.h: Fix prototypes for ld/st functions on 64 bit hosts
The prototypes for the ld/st functions on a 64 bit host declared
the address parameter as a TCGv_i64 rather than a TCGv_ptr. This
worked OK (since the two are aliases), but needs to be fixed to
allow extension of TCG type debugging to i64/i32/ptr mismatches.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 18:26:20 +02:00
Brad
03938c133e Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD.
Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD
to fix compilation of the MIPS host support for OpenBSD/mips64 based architecures.

Signed-off-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 18:23:53 +02:00
Stefan Weil
06ea77bc50 Fix spelling in comment (additon -> addition)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-29 11:58:28 +01:00
Aurelien Jarno
8c11ad25f4 tcg: don't keep dead outputs in registers
If an op with dead outputs is not removed, because it has side effects
or has multiple output and only one dead, mark the registers as dead
instead of saving them. This avoid a few register spills on TCG targets
with low register count, especially with div2 and mul2 ops, or when a
qemu_ld* result is not used (prefetch emulation for example).

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23 22:38:26 +02:00
Aurelien Jarno
6b64b624cd tcg: mark dead output argument in op_dead_args
If an op is not removed and has dead output arguments, mark it
in op_dead_args similarly to what is done for input arguments.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23 22:38:13 +02:00
Aurelien Jarno
866cb6cb21 tcg: replace op_dead_iargs by op_dead_args
Allow all args to be dead by replacing the input specific op_dead_iargs
variable by op_dead_args. Note this is a purely mechanical change.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23 22:38:11 +02:00
Stefan Weil
5225d66921 Fix typos in comments (accross -> across)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-08 10:02:16 +01:00
Peter Maydell
24e838b787 tcg/arm: Support host code being compiled for Thumb
Although the TCG generated code is always in ARM mode, it is possible
that the host code was compiled by gcc in Thumb mode (this is often the
default for Linux distributions targeting ARM v7 only). Handle this
by using BLX imm when doing a call from ARM into Thumb mode.
Since BLX imm is not a conditionalisable instruction, we make
tcg_out_call() no longer take a condition code; we were only ever
using it with COND_AL anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-03-24 03:27:22 +01:00
Peter Maydell
27bfd83c33 tcg: Add support for debugging leakage of temporaries
Add support (if CONFIG_DEBUG_TCG is defined) for debugging leakage
of temporary variables. Generally any temporaries created by
a target while it is translating an instruction should be freed
by the end of that instruction; otherwise carefully crafted
guest code could cause TCG to run out of temporaries and assert.
By calling tcg_check_temp_count() after each instruction we can
check that we are not leaking temporaries in this way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07 09:26:06 +01:00
Edgar E. Iglesias
3a34dfd7f6 tcg: README, name deposit second argument len/LEN
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-20 12:16:57 +01:00
Richard Henderson
b7767f0f3c tcg: Define "deposit" as an optional operation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-20 12:16:05 +01:00
Aurelien Jarno
5677903453 tcg arm/mips/ia64: add a comment about retranslation and caches
Add a comment about cache coherency and retranslation, so that people
developping new targets based on existing ones are warned of the issue.

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12 00:06:07 +01:00
Aurelien Jarno
0f11f25a00 tcg/arm: improve constant loading
Improve constant loading in two ways:
- On all ARM versions, it's possible to load 0xffffff00 = -0x100 using
  the mvn rd, #0. Fix the conditions.
- On <= ARMv6 versions, where movw and movt are not available, load the
  constants using mov and orr with rotations depending on the constant
  to load. This is very useful for example to load constants where the
  low byte is 0. This reduce the generated code size by about 7%.

Also fix the coding style at the same time.

Cc: Andrzej Zaborowski <balrog@zabor.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10 07:30:30 +01:00
Aurelien Jarno
a3e28aa5c7 tcg/ia64: remove an unnecessary stop bit
Spotted by Richard Henderson.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10 01:39:49 +01:00
Mike Frysinger
759c90ba3d tcg: fix typo in readme
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-09 21:01:01 +00:00
Stefan Weil
aa95e3a57f tcg/README: Spelling fixes
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-09 21:00:16 +00:00
Aurelien Jarno
d43ffce140 tcg/mips: fix branch target change during code retranslation
TCG on MIPS was trying to avoid changing the branch offset, but didn't
due to a stupid typo. Fix it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08 16:41:43 +01:00
Aurelien Jarno
9a3abc21a6 tcg/arm: fix qemu_st64 for big endian targets
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of
a 64 bit word before saving it. This patch fixes that.

Acked-by: Andrzej Zaborowski <balrogg@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08 16:41:33 +01:00
Aurelien Jarno
c69806ab82 tcg/arm: fix branch target change during code retranslation
QEMU uses code retranslation to restore the CPU state when an exception
happens. For it to work the retranslation must not modify the generated
code. This is what is currently implemented in ARM TCG.

However on CPU that don't have icache/dcache/memory synchronised like
ARM, this requirement is stronger and code retranslation must not modify
the generated code "atomically", as the cache line might be flushed
at any moment (interrupt, exception, task switching), even if not
triggered by QEMU. The probability for this to happen is very low, and
depends on cache size and associativiy, machine load, interrupts, so the
symptoms are might happen randomly.

This requirement is currently not followed in tcg/arm, for the
load/store code, which basically has the following structure:
  1) tlb access code is written
  2) conditional fast path code is written
  3) branch is written with a temporary target
  4) slow path code is written
  5) branch target is updated
The cache lines corresponding to the retranslated code is not flushed
after code retranslation as the generated code is supposed to be the
same. However if the cache line corresponding to the branch instruction
is flushed between step 3 and 5, and is not flushed again before the
code is executed again, the branch target is wrong. In the guest, the
symptoms are MMU page fault at a random addresses, which leads to
kernel page fault or segmentation faults.

The patch fixes this issue by avoiding writing the branch target until
it is known, that is by writing only the branch instruction first, and
later only the offset.

This fixes booting linux guests on ARM hosts (tested: arm, i386, mips,
mipsel, sh4, sparc).

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08 16:39:47 +01:00
Richard Henderson
393f398b69 tcg-ia64: Fix warning in qemu_ld.
The usermode version of qemu_ld doesn't used mem_index,
leading to set-but-not-used warnings.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
07f59737d8 tcg-ia64: Fix address compilation in qemu_st.
A typo in the usermode address calculation path; R3 used where R2 needed.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
650a217a65 tcg-ia64: Fix tlb read error for 32-bit targets.
Use ld4 not ld8 for reading the tlb of 32-bit targets.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
b3b0091f07 tcg-ia64: Implement qemu_ld32.
The port was not properly merged following
86feb1c860

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
255108c0e3 tcg-ia64: Provide default GUEST_BASE.
Fix compilation error when GUEST_BASE is not defined.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
0909cbde9a tcg: Fix default definition of divu_i32 and remu_i32.
The arguments to tcg_gen_helper32 for these functions were not
updated correctly in rev 2bece2c883.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:30 +01:00
Stefan Weil
405cf9ff00 tcg: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:58 +00:00
Stefan Weil
c3b08d0e05 tcg: Fix compiler error (comparison of unsigned expression)
When qemu is configured with --enable-debug-tcg,
gcc throws this warning (or error with -Werror):

tcg/tcg.c:1030: error: comparison of unsigned expression >= 0 is always true

Fix it by removing the >= 0 part.
The type cast to 'unsigned' catches negative values of op
(which should never happen).

This is a modification of Hollis Blanchard's patch.

Cc: Hollis Blanchard <hollis@penguinppc.org>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-20 20:52:12 +00:00
Andreas Färber
b1d6d51d95 TCG: Revert ppc64 tcg_out_movi32 change
3b6dac3416 apparently broke the ppc64 TCG target
compilation in the code path without guest base.

Reverting this line fixes the build.

Signed-off-by: Andreas F?rber <andreas.faerber@web.de>
Cc: malc <av1474@comtv.ru>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: malc <av1474@comtv.ru>
2010-08-15 00:57:40 +04:00
Andreas Färber
e9119cd864 TCG: Fix Darwin/ppc calling convention recognition
5da79c86a3 broke compilation on Mac OS X v10.5 ppc.
Apple's GCC 4.0.1 does not define _CALL_DARWIN. Recognize __APPLE__ again as well.

Signed-off-by: Andreas F?rber <andreas.faerber@web.de>
Cc: malc <av1474@comtv.ru>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: J?rgen Lock <nox@jelal.kn-bremen.de>
Cc: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: malc <av1474@comtv.ru>
2010-08-15 00:40:42 +04:00
Richard Henderson
48bb3750e1 tcg-s390: new TCG Target
Original patch from Ulrich Hecht, further work from Alexander Graf
and Richard Henderson.

Cc: Ulrich Hecht <uli@suse.de>
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29 23:07:51 +02:00
Richard Henderson
b9e946c781 tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.
We need not reserve the register unless we're going to use it.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: malc <av1474@comtv.ru>
2010-06-29 23:30:36 +04:00
Richard Henderson
2bece2c883 tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments.  Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be
zero-extended to 64-bits.

To effect this, extend the "sizemask" parameter to tcg_gen_callN
to include the signedness of the type of each parameter.  If the
tcg target requires it, extend each 32-bit argument into a 64-bit
temp and pass that to the function call.

This ABI feature is required by sparc64, ppc64 and s390x.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-16 11:29:11 +02:00
Aurelien Jarno
0e2029a063 tcg: fix DEF macro after commit c61aaf7a38
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11 18:39:47 +02:00
Richard Henderson
1bcaae666f tcg-s390: Icache flush is a no-op.
Before gcc 4.2, __builtin___clear_cache doesn't exist, and
afterward the gcc s390 backend implements it as nothing.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11 08:46:05 +02:00
Aurelien Jarno
dc397ca35e tcg-i386: fix andi r, r, 0xff
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10 20:52:47 +02:00
Aurelien Jarno
447d681e8b tcg-i386: remove use of _Bool that slipped code review
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10 20:41:08 +02:00
Richard Henderson
5d8a4f8f4a tcg-i386: Merge 64-bit generation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10 00:16:21 +02:00
Aurelien Jarno
c61aaf7a38 tcg: get rid of DEF2 in tcg-opc.h
Now that tcg-opc.h is only used in TCG code, get rid of DEF2 in
tcg-opc.h.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Aurelien Jarno
239fda311a tcg: get rid of copy_size in TCGOpDef
copy_size is a left-over from the dyngen era, remove it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Richard Henderson
e4d58b41f9 tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 11:18:26 +02:00
Richard Henderson
3b6dac3416 tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter.  This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"
as represented by the existing TCG_TYPE_PTR.

Update all targets to match.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 11:18:25 +02:00
Aurelien Jarno
4309a79bff tcg-i386: fix a typo
Fix a typo introduced by c28b14c694.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-03 00:02:30 +02:00
Aurelien Jarno
c28b14c694 tcg-i386: declare tcg_out_tlb_load() inline
Declare tcg_out_tlb_load() inline so that we don't loose optimisations
with commit 8516a04467.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:51:06 +02:00
Richard Henderson
82bb07db0c tcg-i386: Remove some ifdefs in qemu_ld/st.
Tidy some code by replacing ifdefs by C ifs.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:27 +02:00
Richard Henderson
8516a04467 tcg-i386: Split out tlb load function.
Share some code between qemu_ld and qemu_st.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:26 +02:00
Richard Henderson
1a6dc1e406 tcg-i386: Swap order of TLB hit and miss paths.
Make fallthru be TLB hit and branch be TLB miss.  Doing this
both improves branch prediction and will allow further cleanup.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:26 +02:00
Richard Henderson
be5a4eb7f0 tcg-i386: Split out TLB Hit path from qemu_ld/st.
Splitting out these functions will allow further cleanups.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:26 +02:00
Richard Henderson
96b4cf38f0 tcg-i386: Tidy data16 prefixes.
Include it in the opcode as an extension, as with P_EXT
or the REX bits in the x86-64 port.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:26 +02:00
Richard Henderson
3e1dbaddbf tcg: Use INDEX_op_qemu_ld32 for 32-bit results.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-28 20:54:34 +02:00
Richard Henderson
6781d08d2e tcg-ia64: Load GUEST_BASE into a register.
Saves one bundle per memory operation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
7221f058a6 tcg-ia64: Fix some register usage issues.
(1) The output registers were not marked call-clobbered, even though
    they can be modified by called functions.
(2) The thread pointer was not marked reserved.
(3) R4-R6 are call-saved, but not saved by the prologue.  Rather than
    save them, mark them reserved so that we don't use them.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
4b31713dc4 tcg-hppa: Load GUEST_BASE as an immediate.
Now that the prologue is generated after GUEST_BASE is fixed,
we can load it as an immediate, and also avoid reserving the
register if it isn't necessary.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
9002ec794e tcg: Initialize the prologue after GUEST_BASE is fixed.
This will allow backends to make intelligent choices about how
to implement GUEST_BASE.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
7868652357 tcg-i386: Nuke trailing whitespace.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:23 +00:00
Richard Henderson
5d1e4e85ce tcg-i386: Use lea for three-operand add.
The result is shorter than the mov+add that TCG would
otherwise generate for us.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:23 +00:00
Richard Henderson
34a6d0b7fc tcg-i386: Tidy lea.
Implement full modrm+sib addressing mode processing.
Use that in qemu_ld/st to output the LEA.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
b3e66df71a tcg-i386: Tidy xchg.
Define and use OPC_XCHG_ax_r32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00