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4 Commits

Author SHA1 Message Date
Richard Henderson
7534695b40 target/loongarch: Terminate vmstate subsections list 
This list requires a NULL terminator.

Fixes: 16f5396cec ("target/loongarch: Add LSX data type VReg")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230510062405.127260-1-richard.henderson@linaro.org>
 2023-05-10 09:52:36 +01:00
Song Gao
16f5396cec
target/loongarch: Add LSX data type VReg 
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-2-gaosong@loongson.cn>
 2023-05-06 11:19:42 +08:00
Xiaojuan Yang
7e1c521e2a target/loongarch: Add MMU support for LoongArch CPU. 
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-23-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2022-06-06 18:09:03 +00:00
Xiaojuan Yang
67ebd42a48 target/loongarch: Add basic vmstate description of CPU. 
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-21-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2022-06-06 18:09:03 +00:00