0711c28497
9209 Commits
| Author | SHA1 | Message | Date | |
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Igor Mammedov
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0711c28497 |
tests: qtest: print device_add error before failing test
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20230112140312.3096331-2-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Peter Maydell
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65cc5ccf06 |
Second RISC-V PR for QEMU 8.0
* riscv_htif: Support console output via proxy syscall * Cleanup firmware and device tree loading * Fix elen check when using vector extensions * add RISC-V OpenSBI boot test * Ensure we always follow MISA parsing * Fix up masking of vsip/vsie accesses * Trap on writes to stimecmp from VS when hvictl.VTI=1 * Introduce helper_set_rounding_mode_chkfrm -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmPKRP0ACgkQIeENKd+X cFTHTwgAkyRDxrLepvI0KNaT0+cUBh+3QFlJ5JRtVnDW+5R+3aGT72PTS7Migqoh H3IFCB2mcSdQvyjj2jDFlrFd0oVIaqE0+bnhouS/4nHB5S/vmapHi4Mc74Vv1CMB rgXScL+C5gDOH1I7XjqOb1FY5Vxqyhi3IzdIoj+0ysUrGmUkqx+ij/cfQL7jkH9Q slNAkorgwgrTgMgkJ5RKd4cjyv35O4XKLAsgixVTfJ+WcxKmc/zaJOkNM/UDnmxK k2+2P8bshZWtWscXbm3oMC5+2ow1QtFedEkhHqb4adkQIyolKL7P1TfMlCgMSvES BKl0DUhqQ+7F77tik3GPy9spQ6LpTQ== =ifFF -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu into staging Second RISC-V PR for QEMU 8.0 * riscv_htif: Support console output via proxy syscall * Cleanup firmware and device tree loading * Fix elen check when using vector extensions * add RISC-V OpenSBI boot test * Ensure we always follow MISA parsing * Fix up masking of vsip/vsie accesses * Trap on writes to stimecmp from VS when hvictl.VTI=1 * Introduce helper_set_rounding_mode_chkfrm # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmPKRP0ACgkQIeENKd+X # cFTHTwgAkyRDxrLepvI0KNaT0+cUBh+3QFlJ5JRtVnDW+5R+3aGT72PTS7Migqoh # H3IFCB2mcSdQvyjj2jDFlrFd0oVIaqE0+bnhouS/4nHB5S/vmapHi4Mc74Vv1CMB # rgXScL+C5gDOH1I7XjqOb1FY5Vxqyhi3IzdIoj+0ysUrGmUkqx+ij/cfQL7jkH9Q # slNAkorgwgrTgMgkJ5RKd4cjyv35O4XKLAsgixVTfJ+WcxKmc/zaJOkNM/UDnmxK # k2+2P8bshZWtWscXbm3oMC5+2ow1QtFedEkhHqb4adkQIyolKL7P1TfMlCgMSvES # BKl0DUhqQ+7F77tik3GPy9spQ6LpTQ== # =ifFF # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Jan 2023 07:38:37 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu: (37 commits) hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() target/riscv: Remove helper_set_rod_rounding_mode target/riscv: Introduce helper_set_rounding_mode_chkfrm tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 target/riscv: Fix up masking of vsip/vsie accesses hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() hw/riscv/sifive_u.c: simplify create_fdt() hw/riscv/virt.c: simplify create_fdt() hw/riscv/spike.c: simplify create_fdt() target/riscv: Use TARGET_FMT_lx for env->mhartid target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() target/riscv/cpu: set cpu->cfg in register_cpu_props() hw/riscv/boot.c: use MachineState in riscv_load_kernel() hw/riscv/boot.c: use MachineState in riscv_load_initrd() hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() hw/riscv/spike.c: load initrd right after riscv_load_kernel() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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fcb7e040f5 |
Header cleanup patches for 2023-01-20
-----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmPKN6YSHGFybWJydUBy ZWRoYXQuY29tAAoJEDhwtADrkYZTPeoQAIKl/BF6PFRNq0/k3vPqMe6nltjgkpa/ p7E5qRlo31RCeUB+f0iW26mySnNTgYkE28yy57HxUML/9Lp1bbxyDgRNiJ406a4L kFVF04kOIFez1+mfvWN92DZqcl/EAAqNL6XqSFyO38kYwcsFsi+BZ7DLZbL9Ea8v wVywB96mN6KyrLWCJ2D0OqIVuPHSHol+5zt9e6+ShBgN0FfElLbv0F4KH3VJ1olA psKl6w6V9+c2zV1kT/H+S763m6mQdwtVo/UuOJoElI+Qib/UBxDOrhdYf4Zg7hKf ByUuhJUASm8y9yD/42mFs90B6eUNzLSBC8v1PgRqSqDHtllveP4RysklBlyIMlOs DKtqEuRuIJ/qDXliIFHY6tBnUkeITSd7BCxkQYfaGyaSOcviDSlE3AyaaBC0sY4F P/lTTiRg5ksvhDYtJnW3mSfmT2PY7aBtyE3D1Z84v9hek6D0reMQTE97yL/j4m7P wJP8aM3Z8GILCVxFIh02wmqWZhZUCGsIDS/vxVm+u060n66qtDIQFBoazsFJrCME eWI+qDNDr6xhLegeYajGDM9pdpQc3x0siiuHso4wMSI9NZxwP+tkCVhTpqmrRcs4 GSH/4IlUXqEZdUQDL38DfA22C1TV8BzyMhGLTUERWWYki1sr99yv0pdFyk5r3nLB SURwr58rB2zo =dOfq -----END PGP SIGNATURE----- Merge tag 'pull-include-2023-01-20' of https://repo.or.cz/qemu/armbru into staging Header cleanup patches for 2023-01-20 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmPKN6YSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTPeoQAIKl/BF6PFRNq0/k3vPqMe6nltjgkpa/ # p7E5qRlo31RCeUB+f0iW26mySnNTgYkE28yy57HxUML/9Lp1bbxyDgRNiJ406a4L # kFVF04kOIFez1+mfvWN92DZqcl/EAAqNL6XqSFyO38kYwcsFsi+BZ7DLZbL9Ea8v # wVywB96mN6KyrLWCJ2D0OqIVuPHSHol+5zt9e6+ShBgN0FfElLbv0F4KH3VJ1olA # psKl6w6V9+c2zV1kT/H+S763m6mQdwtVo/UuOJoElI+Qib/UBxDOrhdYf4Zg7hKf # ByUuhJUASm8y9yD/42mFs90B6eUNzLSBC8v1PgRqSqDHtllveP4RysklBlyIMlOs # DKtqEuRuIJ/qDXliIFHY6tBnUkeITSd7BCxkQYfaGyaSOcviDSlE3AyaaBC0sY4F # P/lTTiRg5ksvhDYtJnW3mSfmT2PY7aBtyE3D1Z84v9hek6D0reMQTE97yL/j4m7P # wJP8aM3Z8GILCVxFIh02wmqWZhZUCGsIDS/vxVm+u060n66qtDIQFBoazsFJrCME # eWI+qDNDr6xhLegeYajGDM9pdpQc3x0siiuHso4wMSI9NZxwP+tkCVhTpqmrRcs4 # GSH/4IlUXqEZdUQDL38DfA22C1TV8BzyMhGLTUERWWYki1sr99yv0pdFyk5r3nLB # SURwr58rB2zo # =dOfq # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Jan 2023 06:41:42 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-include-2023-01-20' of https://repo.or.cz/qemu/armbru: include/hw/ppc include/hw/pci-host: Drop extra typedefs include/hw/ppc: Don't include hw/pci-host/pnv_phb.h from pnv.h include/hw/ppc: Supply a few missing includes include/hw/ppc: Split pnv_chip.h off pnv.h include/hw/block: Include hw/block/block.h where needed hw/sparc64/niagara: Use blk_name() instead of open-coding it include/block: Untangle inclusion loops coroutine: Use Coroutine typedef name instead of structure tag coroutine: Split qemu/coroutine-core.h off qemu/coroutine.h coroutine: Clean up superfluous inclusion of qemu/lockable.h coroutine: Move coroutine_fn to qemu/osdep.h, trim includes coroutine: Clean up superfluous inclusion of qemu/coroutine.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Markus Armbruster
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e2c1c34f13 |
include/block: Untangle inclusion loops
We have two inclusion loops:
block/block.h
-> block/block-global-state.h
-> block/block-common.h
-> block/blockjob.h
-> block/block.h
block/block.h
-> block/block-io.h
-> block/block-common.h
-> block/blockjob.h
-> block/block.h
I believe these go back to Emanuele's reorganization of the block API,
merged a few months ago in commit
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Markus Armbruster
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68ba85cecc |
coroutine: Split qemu/coroutine-core.h off qemu/coroutine.h
qemu/coroutine.h and qemu/lockable.h include each other.
They need each other only in macro expansions, so we could simply drop
both inclusions to break the loop, and add suitable includes to files
that expand the macros.
Instead, move a part of qemu/coroutine.h to new qemu/coroutine-core.h
so that qemu/coroutine-core.h doesn't need qemu/lockable.h, and
qemu/lockable.h only needs qemu/coroutine-core.h. Result:
qemu/coroutine.h includes qemu/lockable.h includes
qemu/coroutine-core.h.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20221221131435.3851212-5-armbru@redhat.com>
[Semantic rebase conflict with
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Daniel Henrique Barboza
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db2b9a59ca |
tests/avocado: add RISC-V OpenSBI boot test
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.
The riscv32 'spike' machine isn't bootable at this moment, requiring an
OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that
or add a 'skip' test to remind us about it. To work as a reminder that
we have a riscv32 'spike' test that should be enabled as soon as OpenSBI
QEMU rom receives the fix, we're adding a 'skip' test:
(06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike:
SKIP: requires OpenSBI fix to work
[1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
[2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
Cc: Cleber Rosa <crosa@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Tested-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Peter Maydell
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239b8b0699 |
trivial branch pull request 20230118
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Markus Armbruster
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df4bbc9dcb |
coroutine: Clean up superfluous inclusion of qemu/lockable.h
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20221221131435.3851212-4-armbru@redhat.com> |
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Markus Armbruster
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2379247810 |
coroutine: Clean up superfluous inclusion of qemu/coroutine.h
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20221221131435.3851212-2-armbru@redhat.com> |
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Peter Maydell
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701ed34833 |
* Fix the FreeBSD CI jobs in Gitlab by upgrading the packages in the beginning
* Fix the Haiku VM test by updating it to r1beta4 * Allow "make uninstall" * Rename TARGET_FMT_plx to HWADDR_FMT_plx * Some small qtest fixes/improvements * Check for valid amount of CPUs before starting a secure execution s390x guest -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmPH2JIRHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbUSWRAAk7C6vcVeDL066ftV75qErGcY1lpTF5GA 6rn1EO8wxGUxdjwi5koqqcn7m4LGWJKNnbZkp+7u5h4ni1G6Wu5v5Lnemtb0I5qI M7fTr9QUErK39eV5bPNrZ/Zr4bXRnM6BdYGrTh5d4FZoeIwhjBG/zofWNw/4p11L HLxeG3z3xns5DHQFeMn2v8oapRVWq9h5dIFhWwmEoc0+UBT5cboDM0UnJ8iiZ0Q+ 5AvZVn01iQK/UXGj1iT3JK47jE0P5dregm+h4sd0MUYU1/8LaOIy93YvWk1qI7ID WPJoo9EwqYOYf2lmEfbitgxW5tlp5l/1SGtDXuvkisXmQeMMRB3Dv48nta80sFow PVSwwXqkqbazocsBdFP1tF2cBR/mvRPpVKa+VtF2pu9szCREdfbbt6ERJ2sePUyG MpKhqFV/dPLgcbNgvtUQbyzGBxlieoIRgndYmZwxMIb6uJKmlcJkQg2SYfRAVrri Bdbo0/HdW0IBTn7zFmpVUgEtkpxxpiz1zjPKBA4o/vaTDh44HT1EcFCTZ1HKaUbp iLABMtz5DRS+HJbeIsI8IiCAsIG0r8JRukRrde3k4iEzLq4gt+Df7NIXJtlSIJ+H 8M+JO7c2N4meWuHV7x3xUFGVQxYQQG93m8bWbhgyBtdtoayaN9Fb8XpXXShblXxc ozHrBQe3ciI= =zfXp -----END PGP SIGNATURE----- Merge tag 'pull-request-2023-01-18' of https://gitlab.com/thuth/qemu into staging * Fix the FreeBSD CI jobs in Gitlab by upgrading the packages in the beginning * Fix the Haiku VM test by updating it to r1beta4 * Allow "make uninstall" * Rename TARGET_FMT_plx to HWADDR_FMT_plx * Some small qtest fixes/improvements * Check for valid amount of CPUs before starting a secure execution s390x guest # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmPH2JIRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUSWRAAk7C6vcVeDL066ftV75qErGcY1lpTF5GA # 6rn1EO8wxGUxdjwi5koqqcn7m4LGWJKNnbZkp+7u5h4ni1G6Wu5v5Lnemtb0I5qI # M7fTr9QUErK39eV5bPNrZ/Zr4bXRnM6BdYGrTh5d4FZoeIwhjBG/zofWNw/4p11L # HLxeG3z3xns5DHQFeMn2v8oapRVWq9h5dIFhWwmEoc0+UBT5cboDM0UnJ8iiZ0Q+ # 5AvZVn01iQK/UXGj1iT3JK47jE0P5dregm+h4sd0MUYU1/8LaOIy93YvWk1qI7ID # WPJoo9EwqYOYf2lmEfbitgxW5tlp5l/1SGtDXuvkisXmQeMMRB3Dv48nta80sFow # PVSwwXqkqbazocsBdFP1tF2cBR/mvRPpVKa+VtF2pu9szCREdfbbt6ERJ2sePUyG # MpKhqFV/dPLgcbNgvtUQbyzGBxlieoIRgndYmZwxMIb6uJKmlcJkQg2SYfRAVrri # Bdbo0/HdW0IBTn7zFmpVUgEtkpxxpiz1zjPKBA4o/vaTDh44HT1EcFCTZ1HKaUbp # iLABMtz5DRS+HJbeIsI8IiCAsIG0r8JRukRrde3k4iEzLq4gt+Df7NIXJtlSIJ+H # 8M+JO7c2N4meWuHV7x3xUFGVQxYQQG93m8bWbhgyBtdtoayaN9Fb8XpXXShblXxc # ozHrBQe3ciI= # =zfXp # -----END PGP SIGNATURE----- # gpg: Signature made Wed 18 Jan 2023 11:31:30 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-01-18' of https://gitlab.com/thuth/qemu: s390x/pv: Implement a CGS check helper tests/vm/haiku.x86_64: Update the Haiku VM to Beta 4 tests/qtest/libqos/e1000e: Remove duplicate register definitions tests/qtest/e1000e-test: Fix the code style tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI MAINTAINERS: Remove bouncing mail address from Kamil Rytarowski bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx Makefile: allow 'make uninstall' Upgrade all packages in the FreeBSD VMs to ensure the freshness Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Thomas Huth
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66ef41d29e |
tests/vm/haiku.x86_64: Update the Haiku VM to Beta 4
The old Haiku VM based on Beta 3 does not work anymore since it fails to install the additional packages now that Beta 4 has been released. Thanks to Alexander von Gluck IV for providing a new image based on Beta 4, we can now upgrade the test image in our QEMU CI, too, to get this working again. Note that Haiku Beta 4 apparently finally fixed the issue with the enumeration of the virtio-block devices (see the ticket at https://dev.haiku-os.org/ticket/16512 ) - the tarball disk can now be found at index 1 instead of index 0. Message-Id: <20230116083014.55647-1-thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Akihiko Odaki
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57b8d8d6c2 |
tests/qtest/libqos/e1000e: Remove duplicate register definitions
The register definitions in tests/qtest/libqos/e1000e.h had names different from hw/net/e1000_regs.h, which made it hard to understand what test codes corresponds to the implementation. Use hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove these duplications. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230114035919.35251-20-akihiko.odaki@daynix.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Akihiko Odaki
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da994bac07 |
tests/qtest/e1000e-test: Fix the code style
igb implementation first starts off by copying e1000e code. Correct the code style before that. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230114035919.35251-19-akihiko.odaki@daynix.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Fabiano Rosas
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db2237c459 |
tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI
We will soon enable the build without TCG, which does not support many machines, so only run the bcm2835-dma-test when the corresponding machine is present. Signed-off-by: Fabiano Rosas <farosas@suse.de> Message-Id: <20230113140419.4013-23-farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Stefan Berger
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255b00b4de |
tests/qtest/tpm-emu: Avoid hangs using abort handlers closing channels
Install abort handlers that close the TPM control and data channels in case an abort occurs. The purpose of this is to have QEMU terminate under abnormal test case failures to resolve intermittent hangs on s390x hosts running TPM tests for QEMU/x86_64. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20230111134547.3959604-1-stefanb@linux.ibm.com |
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Stefan Berger
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82df11e78d |
tests/qtest: Poll on waitpid() for a while before sending SIGKILL
To prevent getting stuck on waitpid() in case the target process does not terminate on SIGTERM, poll on waitpid() for 30s and if the target process has not changed state until then send a SIGKILL to it. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20230112143413.3979057-1-stefanb@linux.ibm.com [PMM: changed TFR to RETRY_ON_EINTR] |
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Thomas Huth
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6eb71c6a1e |
tests/qtest/test-hmp: Improve the check for verbose mode
Running the test-hmp with V=2 up to V=9 runs the test in verbose mode, but running for example with V=10 falls back to non-verbose mode ... Improve this oddity by properly treating the argument as a number. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109101306.271444-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu> |
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Guoyi Tu
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0038e9a226 |
Call qemu_socketpair() instead of socketpair() when possible
As qemu_socketpair() was introduced in commit
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Thomas Huth
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fb7e799034 |
tests/qtest/qom-test: Do not print tested properties by default
We're still running into the problem that some logs are cut in the gitlab-CI since they got too big. The biggest part of the log is still the output of the qom-test. Let's stop printing the properties by default to get to a saner size here. The full output can still be enabled by setting V=2 (or higher) in the environment. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221215153036.422362-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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a8d6abe129 |
MIPS patches queue
A bunch of cleanups from various people. - Improved GT64120 on big-endian hosts - GT64120 north bridge and MC146818 RTC devices are now target independent - Bonito64 north bridge converted to 3-phase reset API - PCI refactors around PIIX devices - Support for nanoMIPS in bootloader generator API - New YAMON Malta Avocado test - Removal of 'trap and emulate' KVM support - System-specific QMP commands restricted to system emulation -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmPBekAACgkQ4+MsLN6t wN4wjxAAtYxyt6WUBpiYfV/LnbQFpAsacues1Vhy9MPYEg5a/iuXWKvWtgRYvGww qR0GVQH8rH7tgnCZK+ioq9jX+hvfBskP6CnKhxmb5zDGm7vP7jhhu8UFWY/EtBgq 0zpNeLMXtnRJ6PBqo/nWFCVtcpDRZ6IkSbpGWkVkciRFc5n/2VCnlIj8k2I1oMvL 11cp2xFQnaPReFXIpMjJHuHv1NObykdlvVg6wQo/A/4qIb8EvJQEPmePjG9Sf0i0 v2dhnnxG9mze7+uq0dIC16x8Azko3N7dmtNlBU/aGb9OELwx35aux2M4dNDVogwn DqL/Wsk54TFewECOfS48t/a/TqV8j/ISW1d/JvovBrN2KovmIAbtqHuMUqKVk5l0 23ZOIIPIYwmScZwIlkCIGUuIzFig1zhEmQcoEQaFe/B0oLB2eN/x0Bk9Yklo+i2A WNiyiAj7k5492qEdndOySEEDVt6886F/+CdQ6QYF5Z1L/ELck7XHBH3mGDznWpPn 6IURyVquPJx7ul62jSGI+Gc+qakNoahIhPo5O7hklOM9GwWNOWXHveyb7xjs7j+O eWyVcet+o7hoHkCzmfbyTPySI4qCpF9fA42jqPhATwQPwmGXpbr+4BxUq3KtE43y w9tEigwd4voN3dWLItVh6QE4in70osz3XHp93byvo8bHlS0huVY= =oXX+ -----END PGP SIGNATURE----- Merge tag 'mips-20230113' of https://github.com/philmd/qemu into staging MIPS patches queue A bunch of cleanups from various people. - Improved GT64120 on big-endian hosts - GT64120 north bridge and MC146818 RTC devices are now target independent - Bonito64 north bridge converted to 3-phase reset API - PCI refactors around PIIX devices - Support for nanoMIPS in bootloader generator API - New YAMON Malta Avocado test - Removal of 'trap and emulate' KVM support - System-specific QMP commands restricted to system emulation # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmPBekAACgkQ4+MsLN6t # wN4wjxAAtYxyt6WUBpiYfV/LnbQFpAsacues1Vhy9MPYEg5a/iuXWKvWtgRYvGww # qR0GVQH8rH7tgnCZK+ioq9jX+hvfBskP6CnKhxmb5zDGm7vP7jhhu8UFWY/EtBgq # 0zpNeLMXtnRJ6PBqo/nWFCVtcpDRZ6IkSbpGWkVkciRFc5n/2VCnlIj8k2I1oMvL # 11cp2xFQnaPReFXIpMjJHuHv1NObykdlvVg6wQo/A/4qIb8EvJQEPmePjG9Sf0i0 # v2dhnnxG9mze7+uq0dIC16x8Azko3N7dmtNlBU/aGb9OELwx35aux2M4dNDVogwn # DqL/Wsk54TFewECOfS48t/a/TqV8j/ISW1d/JvovBrN2KovmIAbtqHuMUqKVk5l0 # 23ZOIIPIYwmScZwIlkCIGUuIzFig1zhEmQcoEQaFe/B0oLB2eN/x0Bk9Yklo+i2A # WNiyiAj7k5492qEdndOySEEDVt6886F/+CdQ6QYF5Z1L/ELck7XHBH3mGDznWpPn # 6IURyVquPJx7ul62jSGI+Gc+qakNoahIhPo5O7hklOM9GwWNOWXHveyb7xjs7j+O # eWyVcet+o7hoHkCzmfbyTPySI4qCpF9fA42jqPhATwQPwmGXpbr+4BxUq3KtE43y # w9tEigwd4voN3dWLItVh6QE4in70osz3XHp93byvo8bHlS0huVY= # =oXX+ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Jan 2023 15:35:28 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'mips-20230113' of https://github.com/philmd/qemu: (46 commits) scripts/git.orderfile: Display MAINTAINERS changes first target/mips: Restrict 'qapi-commands-machine.h' to system emulation hw/mips/boston: Rename MachineState 'mc' pointer to 'ms' hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in header hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 code hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge code hw/pci-host/bonito: Convert to 3-phase reset softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818 hw/rtc/mc146818rtc: Make the mc146818 RTC device target independent hw/core/qdev-properties-system: Allow the 'slew' policy only on x86 hw/intc: Extract the IRQ counting functions into a separate file hw/intc/i8259: Make using the isa_pic singleton more type-safe hw/usb/hcd-uhci: Introduce TYPE_ defines for device models hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() hw/pci/pci_host: Trace config accesses on unexisting functions mips: Always include nanomips disassembler mips: Remove support for trap and emulate KVM ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Philippe Mathieu-Daudé
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14c2b18414 |
tests/avocado: Add tests booting YAMON ROM on MIPS Malta machines
Add quick tests booting YAMON: $ avocado --show=app,console run -t machine:malta tests/avocado/machine_mips_malta.py (1/2) tests/avocado/machine_mips_malta.py:MaltaMachine.test_mipsel_malta_yamon: console: YAMON ROM Monitor, Revision 02.22. console: Copyright (c) 1999-2007 MIPS Technologies, Inc. - All Rights Reserved. console: For a list of available commands, type 'help'. console: Compilation time = May 24 2013 12:16:34 (pburton) console: Board type/revision = 0x02 (Malta) / 0x00 console: Core board type/revision = 0x01 (CoreLV) / 0x00 console: System controller/revision = Galileo / GT_64120A-B-0 console: FPGA revision = 0x0000 console: MAC address = ff.ff.ff.ff.ff.ff console: Board S/N = 0123456789 console: PCI bus frequency = 33.33 MHz console: Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x00 console: Processor ID/revision = 0x93 (MIPS 24Kf) / 0x00 console: Endianness = Little console: CPU/Bus frequency = 333 MHz / 419 MHz console: Coherency = None console: Flash memory size = 4 MByte console: SDRAM size = 128 MByte console: First free SDRAM address = 0x800c32f0 console: WARNING: Environment variable flash area is invalid! console: HINT : Perform "erase -e" console: YAMON> PASS (1.88 s) (2/2) tests/avocado/machine_mips_malta.py:MaltaMachine.test_mips64el_malta_yamon: ... console: System controller/revision = Galileo / GT_64120A-B-0 console: Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x00 console: Processor ID/revision = 0x82 (MIPS 20Kc) / 0xa0 ... console: YAMON> PASS (1.89 s) RESULTS : PASS 2 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 4.57 s YAMON does some endian-swapped acceses on the ISD<->PCI CFG/DATA registers. These tests are useful to debug cross-endianness issues, in particular on big-endian host. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230104133935.4639-7-philmd@linaro.org> |
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Strahinja Jankovic
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22bd244a1c |
tests/avocado: Add SD boot test to Cubieboard
Cubieboard now can boot directly from SD card, without the need to pass `-kernel` parameter. Update Avocado tests to cover this functionality. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-8-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Daniel P. Berrangé
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88a0ef00d7 |
enforce use of G_GNUC_PRINTF attributes
We've been very gradually adding G_GNUC_PRINTF annotations to functions over years. This has been useful in detecting certain malformed printf strings, or cases where we pass user data as the printf format which is a potential security flaw. Given the inherant memory corruption danger in use of format strings vs mis-matched variadic arguments, it is worth applying G_GNUC_PRINTF to all functions using printf, even if we know they are safe. The compilers can reasonably reliably identify such places with the -Wsuggest-attribute=format / -Wmissing-format-attribute flags. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20221219130205.687815-7-berrange@redhat.com> [-Wsuggest-attribute=format and -Wmissing-format-attribute are synonyms, only include one; disable it for testfloat. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Daniel P. Berrangé
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0472b2e541 |
tests: add G_GNUC_PRINTF for various functions
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20221219130205.687815-6-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Peter Maydell
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aa96ab7c9d |
* s390x header clean-ups from Philippe
* Rework and improvements of the EINTR handling by Nikita * Deprecate the -no-hpet command line option * Disable the qtests in the 32-bit Windows CI job again * Some other misc fixes here and there -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmO8It8RHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbUwbA//dXgfHy95C1r2nTMDekk09+KkmNB1f6M8 3HK4ROmmrMT/aP9FwfqMBT7JHM/m4bwOGw0Sula8vfjg9NYGPWuSYjdObWKnrIq/ YORoTxqak9c98Co06EQbAfWn3Pj0ifQkX+FIyzcNGhu4856FWdBsMuyq52VLi36q Z8ruSOmclzluoIB3mVYY/s5J7ED2A3K0h39frKLE9FGsKObX10KWj+MZyDHi9oGZ ucTHai12OXgNghjlrwI0BqJziih4NxfIWs0JovSo3cN0at7m57G5JChjR38zTMNT 2Q46tDKoIXesY1GUmVuIgJ5F1Uoshc8Pz5qBSQ5mUbZUQMpivhFrEB666wsYmPd1 M/YwnZ+PFhWjem7p28fKmnmkeATvE0S+vMDifTVZ880nmAbyUm1vFKfqV6r2mBrT p4iXfh/9easFfJWHueU4fBwyMndDGRaCRJnP8KQ5I9yb0WZbt+/0k/y8CQD8Oxr7 dNFFFoY3KnIO9DCRO5Wr+3OqUgtSAQyhBDf5V2wSMCFrwPHKsvWKSbdiWR3Qe4ck 41InWgawB3xx57+vXraDUA10+nBZ1VrM92ObqfLPTFqjLCom6Fm85cG4YFRLIvRt rdlOC+ScpeVpec7MwcHrScGL0HmUgPnShDAo07pRy4oKK+c89sXzdAFf2nYJTAWS WCuChrn7VFM= =D+Yw -----END PGP SIGNATURE----- Merge tag 'pull-request-2023-01-09' of https://gitlab.com/thuth/qemu into staging * s390x header clean-ups from Philippe * Rework and improvements of the EINTR handling by Nikita * Deprecate the -no-hpet command line option * Disable the qtests in the 32-bit Windows CI job again * Some other misc fixes here and there # gpg: Signature made Mon 09 Jan 2023 14:21:19 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-01-09' of https://gitlab.com/thuth/qemu: .gitlab-ci.d/windows: Do not run the qtests in the msys2-32bit job error handling: Use RETRY_ON_EINTR() macro where applicable Refactoring: refactor TFR() macro to RETRY_ON_EINTR() docs/interop: Change the vnc-ledstate-Pseudo-encoding doc into .rst i386: Deprecate the -no-hpet QEMU command line option tests/qtest/bios-tables-test: Replace -no-hpet with hpet=off machine parameter tests/readconfig: spice doesn't support unix socket on windows yet target/s390x: Restrict sysemu/reset.h to system emulation target/s390x/tcg/excp_helper: Restrict system headers to sysemu target/s390x/tcg/misc_helper: Remove unused "memory.h" include hw/s390x/pv: Restrict Protected Virtualization to sysemu exec/memory: Expose memory_region_access_valid() MAINTAINERS: Add MIPS-related docs and configs to the MIPS architecture section tests/vm: Update get_default_jobs() to work on non-x86_64 non-KVM hosts qemu-iotests/stream-under-throttle: do not shutdown QEMU Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Nikita Ivanov
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37b0b24e93 |
error handling: Use RETRY_ON_EINTR() macro where applicable
There is a defined RETRY_ON_EINTR() macro in qemu/osdep.h which handles the same while loop. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/415 Signed-off-by: Nikita Ivanov <nivanov@cloudlinux.com> Message-Id: <20221023090422.242617-3-nivanov@cloudlinux.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> [thuth: Dropped the hunk that changed socket_accept() in libqtest.c] Signed-off-by: Thomas Huth <thuth@redhat.com> |
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|
Nikita Ivanov
|
8b6aa69365 |
Refactoring: refactor TFR() macro to RETRY_ON_EINTR()
Rename macro name to more transparent one and refactor it to expression. Signed-off-by: Nikita Ivanov <nivanov@cloudlinux.com> Message-Id: <20221023090422.242617-2-nivanov@cloudlinux.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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|
Thomas Huth
|
9a2112f9ae |
tests/qtest/bios-tables-test: Replace -no-hpet with hpet=off machine parameter
We are going to deprecate (and finally remove later) the -no-hpet command line option. Prepare the bios-tables-test by using the replacement hpet=off machine parameter instead. Message-Id: <20230109081205.116369-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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|
Marc-André Lureau
|
beecc4b78d |
tests/readconfig: spice doesn't support unix socket on windows yet
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20230103110814.3726795-6-marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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|
Philippe Mathieu-Daudé
|
44c8a6ab45 |
tests/vm: Update get_default_jobs() to work on non-x86_64 non-KVM hosts
On non-x86_64 host, if KVM is not available we get:
Traceback (most recent call last):
File "tests/vm/basevm.py", line 634, in main
vm = vmcls(args, config=config)
File "tests/vm/basevm.py", line 104, in __init__
mem = max(4, args.jobs)
TypeError: '>' not supported between instances of 'NoneType' and 'int'
Fix by always returning a -- not ideal but safe -- '1' value.
Fixes:
|
||
|
Christian Borntraeger
|
ad302b21aa |
qemu-iotests/stream-under-throttle: do not shutdown QEMU
Without a kernel or boot disk a QEMU on s390 will exit (usually with a disabled wait state). This breaks the stream-under-throttle test case. Do not exit qemu if on s390. Signed-off-by: Christian Borntraeger <borntraeger@linux.ibm.com> Message-Id: <20221207131452.8455-1-borntraeger@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Peter Maydell
|
d6271b6572 |
virtio,pc,pci: features, cleanups, fixes
mostly vhost-vdpa:
guest announce feature emulation when using shadow virtqueue
support for configure interrupt
startup speed ups
an acpi change to only generate cluster node in PPTT when specified for arm
misc fixes, cleanups
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, cleanups, fixes
mostly vhost-vdpa:
guest announce feature emulation when using shadow virtqueue
support for configure interrupt
startup speed ups
an acpi change to only generate cluster node in PPTT when specified for arm
misc fixes, cleanups
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Sun 08 Jan 2023 08:01:39 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (50 commits)
vhost-scsi: fix memleak of vsc->inflight
acpi: cpuhp: fix guest-visible maximum access size to the legacy reg block
tests: acpi: aarch64: Add *.topology tables
tests: acpi: aarch64: Add topology test for aarch64
tests: acpi: Add and whitelist *.topology blobs
tests: virt: Update expected ACPI tables for virt test
hw/acpi/aml-build: Only generate cluster node in PPTT when specified
tests: virt: Allow changes to PPTT test table
virtio-pci: fix proxy->vector_irqfd leak in virtio_pci_set_guest_notifiers
vdpa: commit all host notifier MRs in a single MR transaction
vhost: configure all host notifiers in a single MR transaction
vhost: simplify vhost_dev_enable_notifiers
vdpa: harden the error path if get_iova_range failed
vdpa-dev: get iova range explicitly
docs/devel: Rules on #include in headers
include: Include headers where needed
include/hw/virtio: Break inclusion loop
include/hw/cxl: Break inclusion loop cxl_pci.h and cxl_cdat_h
include/hw/pci: Include hw/pci/pci.h where needed
include/hw/pci: Split pci_device.h off pci.h
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
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|
Peter Maydell
|
3d83b78285 |
* Atomic memslot updates for KVM (Emanuele, David)
* Always send errors to logfile when daemonized (Greg) * Add support for IDE CompactFlash card (Lubomir) * First round of build system cleanups (myself) * First round of feature removals (myself) * Reduce "qemu/accel.h" inclusion (Philippe) -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmO3Ym0UHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroNYmwf+LHEw+4T0fk1+2NfgIzH3+8s1EqDm Ai56EjxO/p5NUptflXAnhn4P3LawswmmNE0ZIFFFBgwG5E9L+Jj/u5efuLu4uYPg bboEBDn8nxSNN2l08u9TyS6kSWSxbwwrs7i2+V+4uQIlVIcCHu+A0vpXns4vWwY0 zZGF8CgJKDQdPIxdXrH8+6/xtadQ8uDkYsAWDiY/nhozCsCUTAZGTXWEQbHJLARI Z4X+Cmz/NFB9G4ka6K/y0HbQw99KA8G/EMPUSglN0ya10yjpyzrmeI7IlIves+5U 8lhCZXyBhaV9GXlIK1vIgEXlHf83C19a+v0DpW0bpxK631n2VR5y3CArBg== =2Koq -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * Atomic memslot updates for KVM (Emanuele, David) * Always send errors to logfile when daemonized (Greg) * Add support for IDE CompactFlash card (Lubomir) * First round of build system cleanups (myself) * First round of feature removals (myself) * Reduce "qemu/accel.h" inclusion (Philippe) # gpg: Signature made Thu 05 Jan 2023 23:51:09 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (24 commits) i386: SGX: remove deprecated member of SGXInfo target/i386: Add SGX aex-notify and EDECCSSA support util: remove support -chardev tty and -chardev parport util: remove support for hex numbers with a scaling suffix KVM: remove support for kernel-irqchip=off docs: do not talk about past removal as happening in the future meson: accept relative symlinks in "meson introspect --installed" data meson: cleanup compiler detection meson: support meson 0.64 -Doptimization=plain configure: test all warnings tests/qapi-schema: remove Meson workaround meson: cleanup dummy-cpus.c rules meson: tweak hardening options for Windows configure: remove backwards-compatibility and obsolete options configure: preserve qemu-ga variables configure: cleanup $cpu tests configure: remove dead function configure: remove useless write_c_skeleton ide: Add "ide-cf" driver, a CompactFlash card ide: Add 8-bit data mode ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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|
Yicong Yang
|
30f71c4afb |
tests: acpi: aarch64: Add *.topology tables
Add *.topology tables for the aarch64's topology test and empty bios-tables-test-allowed-diff.h The disassembled differences between actual and expected PPTT (the table which we actually care about): +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20180105 (64-bit version) + * Copyright (c) 2000 - 2018 Intel Corporation + * + * Disassembly of /tmp/aml-WUN4U1, Tue Nov 1 09:51:52 2022 + * + * ACPI Data Table [PPTT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "PPTT" [Processor Properties Topology Table] +[004h 0004 4] Table Length : 00000150 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 7C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + + +[024h 0036 1] Subtable Type : 00 [Processor Hierarchy Node] +[025h 0037 1] Length : 14 +[026h 0038 2] Reserved : 0000 +[028h 0040 4] Flags (decoded below) : 00000001 + Physical package : 1 + ACPI Processor ID valid : 0 +[02Ch 0044 4] Parent : 00000000 +[030h 0048 4] ACPI Processor ID : 00000000 +[034h 0052 4] Private Resource Number : 00000000 + +[038h 0056 1] Subtable Type : 00 [Processor Hierarchy Node] +[039h 0057 1] Length : 14 +[03Ah 0058 2] Reserved : 0000 +[03Ch 0060 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[040h 0064 4] Parent : 00000024 +[044h 0068 4] ACPI Processor ID : 00000000 +[048h 0072 4] Private Resource Number : 00000000 + +[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Node] +[04Dh 0077 1] Length : 14 +[04Eh 0078 2] Reserved : 0000 +[050h 0080 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[054h 0084 4] Parent : 00000038 +[058h 0088 4] ACPI Processor ID : 00000000 +[05Ch 0092 4] Private Resource Number : 00000000 + +[060h 0096 1] Subtable Type : 00 [Processor Hierarchy Node] +[061h 0097 1] Length : 14 +[062h 0098 2] Reserved : 0000 +[064h 0100 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[068h 0104 4] Parent : 0000004C +[06Ch 0108 4] ACPI Processor ID : 00000000 +[070h 0112 4] Private Resource Number : 00000000 + +[074h 0116 1] Subtable Type : 00 [Processor Hierarchy Node] +[075h 0117 1] Length : 14 +[076h 0118 2] Reserved : 0000 +[078h 0120 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[07Ch 0124 4] Parent : 0000004C +[080h 0128 4] ACPI Processor ID : 00000001 +[084h 0132 4] Private Resource Number : 00000000 + +[088h 0136 1] Subtable Type : 00 [Processor Hierarchy Node] +[089h 0137 1] Length : 14 +[08Ah 0138 2] Reserved : 0000 +[08Ch 0140 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[090h 0144 4] Parent : 00000038 +[094h 0148 4] ACPI Processor ID : 00000001 +[098h 0152 4] Private Resource Number : 00000000 + +[09Ch 0156 1] Subtable Type : 00 [Processor Hierarchy Node] +[09Dh 0157 1] Length : 14 +[09Eh 0158 2] Reserved : 0000 +[0A0h 0160 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[0A4h 0164 4] Parent : 00000088 +[0A8h 0168 4] ACPI Processor ID : 00000002 +[0ACh 0172 4] Private Resource Number : 00000000 + +[0B0h 0176 1] Subtable Type : 00 [Processor Hierarchy Node] +[0B1h 0177 1] Length : 14 +[0B2h 0178 2] Reserved : 0000 +[0B4h 0180 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[0B8h 0184 4] Parent : 00000088 +[0BCh 0188 4] ACPI Processor ID : 00000003 +[0C0h 0192 4] Private Resource Number : 00000000 + +[0C4h 0196 1] Subtable Type : 00 [Processor Hierarchy Node] +[0C5h 0197 1] Length : 14 +[0C6h 0198 2] Reserved : 0000 +[0C8h 0200 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[0CCh 0204 4] Parent : 00000024 +[0D0h 0208 4] ACPI Processor ID : 00000001 +[0D4h 0212 4] Private Resource Number : 00000000 + +[0D8h 0216 1] Subtable Type : 00 [Processor Hierarchy Node] +[0D9h 0217 1] Length : 14 +[0DAh 0218 2] Reserved : 0000 +[0DCh 0220 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[0E0h 0224 4] Parent : 000000C4 +[0E4h 0228 4] ACPI Processor ID : 00000000 +[0E8h 0232 4] Private Resource Number : 00000000 + +[0ECh 0236 1] Subtable Type : 00 [Processor Hierarchy Node] +[0EDh 0237 1] Length : 14 +[0EEh 0238 2] Reserved : 0000 +[0F0h 0240 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[0F4h 0244 4] Parent : 000000D8 +[0F8h 0248 4] ACPI Processor ID : 00000004 +[0FCh 0252 4] Private Resource Number : 00000000 + +[100h 0256 1] Subtable Type : 00 [Processor Hierarchy Node] +[101h 0257 1] Length : 14 +[102h 0258 2] Reserved : 0000 +[104h 0260 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[108h 0264 4] Parent : 000000D8 +[10Ch 0268 4] ACPI Processor ID : 00000005 +[110h 0272 4] Private Resource Number : 00000000 + +[114h 0276 1] Subtable Type : 00 [Processor Hierarchy Node] +[115h 0277 1] Length : 14 +[116h 0278 2] Reserved : 0000 +[118h 0280 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[11Ch 0284 4] Parent : 000000C4 +[120h 0288 4] ACPI Processor ID : 00000001 +[124h 0292 4] Private Resource Number : 00000000 + +[128h 0296 1] Subtable Type : 00 [Processor Hierarchy Node] +[129h 0297 1] Length : 14 +[12Ah 0298 2] Reserved : 0000 +[12Ch 0300 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[130h 0304 4] Parent : 00000114 +[134h 0308 4] ACPI Processor ID : 00000006 +[138h 0312 4] Private Resource Number : 00000000 + +[13Ch 0316 1] Subtable Type : 00 [Processor Hierarchy Node] +[13Dh 0317 1] Length : 14 +[13Eh 0318 2] Reserved : 0000 +[140h 0320 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[144h 0324 4] Parent : 00000114 +[148h 0328 4] ACPI Processor ID : 00000007 +[14Ch 0332 4] Private Resource Number : 00000000 + +Raw Table Data: Length 336 (0x150) + + 0000: 50 50 54 54 50 01 00 00 02 7C 42 4F 43 48 53 20 // PPTTP....|BOCHS + 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC + 0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................ + 0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $............... + 0050: 00 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8........... + 0060: 00 14 00 00 0E 00 00 00 4C 00 00 00 00 00 00 00 // ........L....... + 0070: 00 00 00 00 00 14 00 00 0E 00 00 00 4C 00 00 00 // ............L... + 0080: 01 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................ + 0090: 38 00 00 00 01 00 00 00 00 00 00 00 00 14 00 00 // 8............... + 00A0: 0E 00 00 00 88 00 00 00 02 00 00 00 00 00 00 00 // ................ + 00B0: 00 14 00 00 0E 00 00 00 88 00 00 00 03 00 00 00 // ................ + 00C0: 00 00 00 00 00 14 00 00 00 00 00 00 24 00 00 00 // ............$... + 00D0: 01 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................ + 00E0: C4 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // ................ + 00F0: 0E 00 00 00 D8 00 00 00 04 00 00 00 00 00 00 00 // ................ + 0100: 00 14 00 00 0E 00 00 00 D8 00 00 00 05 00 00 00 // ................ + 0110: 00 00 00 00 00 14 00 00 00 00 00 00 C4 00 00 00 // ................ + 0120: 01 00 00 00 00 00 00 00 00 14 00 00 0E 00 00 00 // ................ + 0130: 14 01 00 00 06 00 00 00 00 00 00 00 00 14 00 00 // ................ + 0140: 0E 00 00 00 14 01 00 00 07 00 00 00 00 00 00 00 // ................ Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Message-Id: <20221229065513.55652-7-yangyicong@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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|
Yicong Yang
|
46bda3e4de |
tests: acpi: aarch64: Add topology test for aarch64
Add test for aarch64's ACPI topology building for all the supported levels. Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Tested-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Message-Id: <20221229065513.55652-6-yangyicong@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Yicong Yang
|
47a86db4b4 |
tests: acpi: Add and whitelist *.topology blobs
Add and whitelist *.topology blobs, prepares for the aarch64's ACPI topology building test. Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Message-Id: <20221229065513.55652-5-yangyicong@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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|
Yicong Yang
|
e7d0bec940 |
tests: virt: Update expected ACPI tables for virt test
Update the ACPI tables according to the acpi aml_build change, also
empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180105 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/PPTT, Tue Nov 1 09:29:12 2022
+ * Disassembly of /tmp/aml-DIIGV1, Tue Nov 1 09:29:12 2022
*
* ACPI Data Table [PPTT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "PPTT" [Processor Properties Topology Table]
-[004h 0004 4] Table Length : 00000060
+[004h 0004 4] Table Length : 0000004C
[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : 48
+[009h 0009 1] Checksum : A8
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 1] Subtable Type : 00 [Processor Hierarchy Node]
[025h 0037 1] Length : 14
[026h 0038 2] Reserved : 0000
[028h 0040 4] Flags (decoded below) : 00000001
Physical package : 1
ACPI Processor ID valid : 0
[02Ch 0044 4] Parent : 00000000
[030h 0048 4] ACPI Processor ID : 00000000
[034h 0052 4] Private Resource Number : 00000000
[038h 0056 1] Subtable Type : 00 [Processor Hierarchy Node]
[039h 0057 1] Length : 14
[03Ah 0058 2] Reserved : 0000
-[03Ch 0060 4] Flags (decoded below) : 00000000
+[03Ch 0060 4] Flags (decoded below) : 0000000A
Physical package : 0
- ACPI Processor ID valid : 0
+ ACPI Processor ID valid : 1
[040h 0064 4] Parent : 00000024
[044h 0068 4] ACPI Processor ID : 00000000
[048h 0072 4] Private Resource Number : 00000000
-[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Node]
-[04Dh 0077 1] Length : 14
-[04Eh 0078 2] Reserved : 0000
-[050h 0080 4] Flags (decoded below) : 0000000A
- Physical package : 0
- ACPI Processor ID valid : 1
-[054h 0084 4] Parent : 00000038
-[058h 0088 4] ACPI Processor ID : 00000000
-[05Ch 0092 4] Private Resource Number : 00000000
-
-Raw Table Data: Length 96 (0x60)
+Raw Table Data: Length 76 (0x4C)
- 0000: 50 50 54 54 60 00 00 00 02 48 42 4F 43 48 53 20 // PPTT`....HBOCHS
+ 0000: 50 50 54 54 4C 00 00 00 02 A8 42 4F 43 48 53 20 // PPTTL.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................
- 0030: 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................
- 0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $...............
- 0050: 0A 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8...........
+ 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ................
+ 0040: 24 00 00 00 00 00 00 00 00 00 00 00 // $...........
PPTT.acpihmatvirt is also updated:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180105 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/PPTT.acpihmatvirt, Wed Dec 28 15:36:06 2022
+ * Disassembly of /tmp/aml-IPKJX1, Wed Dec 28 15:36:06 2022
*
* ACPI Data Table [PPTT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "PPTT" [Processor Properties Topology Table]
-[004h 0004 4] Table Length : 000000C4
+[004h 0004 4] Table Length : 0000009C
[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : 9E
+[009h 0009 1] Checksum : FE
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 1] Subtable Type : 00 [Processor Hierarchy Node]
[025h 0037 1] Length : 14
[026h 0038 2] Reserved : 0000
[028h 0040 4] Flags (decoded below) : 00000001
Physical package : 1
ACPI Processor ID valid : 0
[02Ch 0044 4] Parent : 00000000
[030h 0048 4] ACPI Processor ID : 00000000
[034h 0052 4] Private Resource Number : 00000000
[038h 0056 1] Subtable Type : 00 [Processor Hierarchy Node]
[039h 0057 1] Length : 14
[03Ah 0058 2] Reserved : 0000
-[03Ch 0060 4] Flags (decoded below) : 00000000
+[03Ch 0060 4] Flags (decoded below) : 0000000A
Physical package : 0
- ACPI Processor ID valid : 0
+ ACPI Processor ID valid : 1
[040h 0064 4] Parent : 00000024
[044h 0068 4] ACPI Processor ID : 00000000
[048h 0072 4] Private Resource Number : 00000000
[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Node]
[04Dh 0077 1] Length : 14
[04Eh 0078 2] Reserved : 0000
[050h 0080 4] Flags (decoded below) : 0000000A
Physical package : 0
ACPI Processor ID valid : 1
-[054h 0084 4] Parent : 00000038
-[058h 0088 4] ACPI Processor ID : 00000000
+[054h 0084 4] Parent : 00000024
+[058h 0088 4] ACPI Processor ID : 00000001
[05Ch 0092 4] Private Resource Number : 00000000
[060h 0096 1] Subtable Type : 00 [Processor Hierarchy Node]
[061h 0097 1] Length : 14
[062h 0098 2] Reserved : 0000
-[064h 0100 4] Flags (decoded below) : 0000000A
- Physical package : 0
- ACPI Processor ID valid : 1
-[068h 0104 4] Parent : 00000038
+[064h 0100 4] Flags (decoded below) : 00000001
+ Physical package : 1
+ ACPI Processor ID valid : 0
+[068h 0104 4] Parent : 00000000
[06Ch 0108 4] ACPI Processor ID : 00000001
[070h 0112 4] Private Resource Number : 00000000
[074h 0116 1] Subtable Type : 00 [Processor Hierarchy Node]
[075h 0117 1] Length : 14
[076h 0118 2] Reserved : 0000
-[078h 0120 4] Flags (decoded below) : 00000001
- Physical package : 1
- ACPI Processor ID valid : 0
-[07Ch 0124 4] Parent : 00000000
-[080h 0128 4] ACPI Processor ID : 00000001
+[078h 0120 4] Flags (decoded below) : 0000000A
+ Physical package : 0
+ ACPI Processor ID valid : 1
+[07Ch 0124 4] Parent : 00000060
+[080h 0128 4] ACPI Processor ID : 00000002
[084h 0132 4] Private Resource Number : 00000000
[088h 0136 1] Subtable Type : 00 [Processor Hierarchy Node]
[089h 0137 1] Length : 14
[08Ah 0138 2] Reserved : 0000
-[08Ch 0140 4] Flags (decoded below) : 00000000
- Physical package : 0
- ACPI Processor ID valid : 0
-[090h 0144 4] Parent : 00000074
-[094h 0148 4] ACPI Processor ID : 00000000
-[098h 0152 4] Private Resource Number : 00000000
-
-[09Ch 0156 1] Subtable Type : 00 [Processor Hierarchy Node]
-[09Dh 0157 1] Length : 14
-[09Eh 0158 2] Reserved : 0000
-[0A0h 0160 4] Flags (decoded below) : 0000000A
- Physical package : 0
- ACPI Processor ID valid : 1
-[0A4h 0164 4] Parent : 00000088
-[0A8h 0168 4] ACPI Processor ID : 00000002
-[0ACh 0172 4] Private Resource Number : 00000000
-
-[0B0h 0176 1] Subtable Type : 00 [Processor Hierarchy Node]
-[0B1h 0177 1] Length : 14
-[0B2h 0178 2] Reserved : 0000
-[0B4h 0180 4] Flags (decoded below) : 0000000A
+[08Ch 0140 4] Flags (decoded below) : 0000000A
Physical package : 0
ACPI Processor ID valid : 1
-[0B8h 0184 4] Parent : 00000088
-[0BCh 0188 4] ACPI Processor ID : 00000003
-[0C0h 0192 4] Private Resource Number : 00000000
+[090h 0144 4] Parent : 00000060
+[094h 0148 4] ACPI Processor ID : 00000003
+[098h 0152 4] Private Resource Number : 00000000
-Raw Table Data: Length 196 (0xC4)
+Raw Table Data: Length 156 (0x9C)
- 0000: 50 50 54 54 C4 00 00 00 02 9E 42 4F 43 48 53 20 // PPTT......BOCHS
+ 0000: 50 50 54 54 9C 00 00 00 02 FE 42 4F 43 48 53 20 // PPTT......BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................
- 0030: 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ................
0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $...............
- 0050: 0A 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8...........
- 0060: 00 14 00 00 0A 00 00 00 38 00 00 00 01 00 00 00 // ........8.......
- 0070: 00 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................
- 0080: 01 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................
- 0090: 74 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // t...............
- 00A0: 0A 00 00 00 88 00 00 00 02 00 00 00 00 00 00 00 // ................
- 00B0: 00 14 00 00 0A 00 00 00 88 00 00 00 03 00 00 00 // ................
- 00C0: 00 00 00 00 // ....
+ 0050: 0A 00 00 00 24 00 00 00 01 00 00 00 00 00 00 00 // ....$...........
+ 0060: 00 14 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0070: 00 00 00 00 00 14 00 00 0A 00 00 00 60 00 00 00 // ............`...
+ 0080: 02 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ................
+ 0090: 60 00 00 00 03 00 00 00 00 00 00 00 // `...........
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Message-Id: <20221229065513.55652-4-yangyicong@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
||
|
Yicong Yang
|
3cce48d333 |
tests: virt: Allow changes to PPTT test table
Allow changes to test/data/acpi/virt/PPTT*, prepare to change the building policy of the cluster topology. Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Message-Id: <20221229065513.55652-2-yangyicong@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Markus Armbruster
|
edf5ca5dbe |
include/hw/pci: Split pci_device.h off pci.h
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Peter Maydell
|
052e6534c4 |
First RISC-V PR for QEMU 8.0
* Fix PMP propagation for tlb * Collection of bug fixes * Bump the OpenTitan supported version * Add smstateen support * Support native debug icount trigger * Remove the redundant ipi-id property in the virt machine * Support cache-related PMU events in virtual mode * Add some missing PolarFire SoC io regions * Fix mret exception cause when no pmp rule is configured * Fix bug where disabling compressed instructions would crash QEMU * Add Zawrs ISA extension support * A range of code refactoring and cleanups -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmO3b5sACgkQIeENKd+X cFTD8Af+L0OaGzE4C0jil7LdITFKk7ltdTg3yw84ZBvIxrEWMWlt5Yj3Ez5OIPbY WpPmCLoJ9XM/5CV5PuPjxcFFExWjXLNeMEvaaT/3/3jPPnA/M/AbZa4hefKRluTg kkvBiOuRMPXiYLki5xAHmjD/1j6SQ8ghylPLxYQqyGq87WZt4Dx9msOTZLVzmmYl 8y9oC8j6yO2UBZYC1TxSkKxFbj+Cp2HmtBZ09tDzwRL6DpRvIlfftiLl8X3awMlK YTzCIrmllc38/+cV9IpQhdXzDUZ1kM7Zy56JbJl3XOsS4VnUYGmEtrKYpYQ2CKLY /tcmrDKNw1ArWcP1axNN8FHfhy1FyQ== =SH+C -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging First RISC-V PR for QEMU 8.0 * Fix PMP propagation for tlb * Collection of bug fixes * Bump the OpenTitan supported version * Add smstateen support * Support native debug icount trigger * Remove the redundant ipi-id property in the virt machine * Support cache-related PMU events in virtual mode * Add some missing PolarFire SoC io regions * Fix mret exception cause when no pmp rule is configured * Fix bug where disabling compressed instructions would crash QEMU * Add Zawrs ISA extension support * A range of code refactoring and cleanups # gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits) hw/intc: sifive_plic: Fix the pending register range check hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC hw/intc: sifive_plic: Update "num-sources" property default value hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() hw/intc: sifive_plic: Improve robustness of the PLIC config parser hw/intc: sifive_plic: Drop PLICMode_H hw/riscv: spike: Remove misleading comments hw/riscv: Sort machines Kconfig options in alphabetical order hw/riscv: Fix opentitan dependency to SIFIVE_PLIC hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC RISC-V: Add Zawrs ISA extension support target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ target/riscv: Simplify helper_sret() a little bit target/riscv: Set pc_succ_insn for !rvc illegal insn ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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aaa90fede5 |
Fix race conditions in new user-only vma tracking.
Add tcg backend paired register allocation. Cleanup tcg backend function call abi. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmO3kZEdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/JpwgAj9kwpiWehGWrpQp9 rbEL+Fsx+SDhnoLVpF6nmSB1nkDqdgkdnhyRaLX9wM69bnocsGppZ5sd57J/cH3m WiODVVbWP80WHonx5EN4htQv99TZWqVmXVl11DwOfsRUmINl4GG4kvHOOABd8hdc 39eRgGBBMyMShc6MUJiToyjEAcZPcGAiHkSW9YDGbvzhlloNWh46eLP1bdW3UJWK UiEwPpXqg+L0V8nuuQnSFoPr5FIJmmoTeiGCRHXtvgOT7J8/6eKUESpfcKkHq1ye dwcJQATuZip3+hyCCVveiZ86TQ81RMp9en1qw+HVzfed1Ial3Tk+tqiDqZJFm25b GMpa5g== =OjPl -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into staging Fix race conditions in new user-only vma tracking. Add tcg backend paired register allocation. Cleanup tcg backend function call abi. # gpg: Signature made Fri 06 Jan 2023 03:12:17 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu: (47 commits) tests/tcg/multiarch: add vma-pthread.c accel/tcg: Handle false negative lookup in page_check_range accel/tcg: Use g_free_rcu for user-exec interval trees accel/tcg: Fix tb_invalidate_phys_page_unwind tcg: Add TCGHelperInfo argument to tcg_out_call tcg/aarch64: Merge tcg_out_callr into tcg_out_call tcg: Move ffi_cif pointer into TCGHelperInfo tcg: Factor init_ffi_layouts() out of tcg_context_init() tcg: Convert typecode_to_ffi from array to function tcg: Reorg function calls tcg: Use output_pref wrapper function tcg: Vary the allocation size for TCGOp tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*() accel/tcg/plugin: Use copy_op in append_{udata,mem}_cb accel/tcg/plugin: Avoid duplicate copy in copy_call accel/tcg/plugin: Don't search for the function pointer index tcg: Use TCG_CALL_ARG_EVEN for TCI special case tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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171033e8db |
Hexagon update: patches from several folks
-----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmO3Cl8ACgkQewJE+xLe RCKopQf/eVpmA04C792MIYHJnAaASbXZ1FA2Q33l9zrPt9V5oL0cer+rNPlqwVIb jUdFLrT6ppe3jgkzeZVzLTGoNiLO1BnpH3+NV5ZpnMBON4g6/uyagRJekvb5xcDw a832LM77zWrSQbV+Z3C0sn87j7u0YFYiXtya3mJUv6iSfKZnR4bGZH+LW2dOrnXn +uMGnjjUQ2Ac7mvHTnrtooVUNhgRpTq4tMBwl1mE/hacUuejBjDgMLHDb6e4yPC7 g0/BuMB1ygBYFDINJ9El5oD0JtYHZjHOX4TKs6i0oXntoeveut62oGRwgLrk8eRe lwKiEvFNrz/RYmCIy8Pz7s+5HQUgqA== =/i3r -----END PGP SIGNATURE----- Merge tag 'pull-hex-20230105' of https://github.com/quic/qemu into staging Hexagon update: patches from several folks # gpg: Signature made Thu 05 Jan 2023 17:35:27 GMT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230105' of https://github.com/quic/qemu: Update scripts/meson-buildoptions.sh Hexagon (target/hexagon) implement mutability mask for GPRs target/hexagon: suppress unused variable warning target/hexagon/idef-parser: fix two typos in README tests/tcg/hexagon: fix underspecifed asm constraints target/hexagon: rename aliased register HEX_REG_P3_0 linux-user/hexagon: fix signal context save & restore Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Richard Henderson
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ec2918b467 |
target/riscv: Set pc_succ_insn for !rvc illegal insn
Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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Paolo Bonzini
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8b902e3d23 |
util: remove support for hex numbers with a scaling suffix
This was deprecated in 6.0 and can now be removed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Paolo Bonzini
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7bef93ff06 |
tests/qapi-schema: remove Meson workaround
The referenced issue has been fixed since version 0.61, so remove the workaround. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Peter Maydell
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d365cb0b9d |
target-arm queue:
* Implement AArch32 ARMv8-R support * Add Cortex-R52 CPU * fix handling of HLT semihosting in system mode * hw/timer/ixm_epit: cleanup and fix bug in compare handling * target/arm: Coding style fixes * target/arm: Clean up includes * nseries: minor code cleanups * target/arm: align exposed ID registers with Linux * hw/arm/smmu-common: remove unnecessary inlines * i.MX7D: Handle GPT timers * i.MX7D: Connect IRQs to GPIO devices * i.MX6UL: Add a specific GPT timer instance * hw/net: Fix read of uninitialized memory in imx_fec -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmO2/iYZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3sy1EACPsxR5R19BbfwuR3e2VKrA 3ltc1ZwiEiDzKE0YJ+VL8zSyzNKFs0OD4O+ZOBPu5PegwhLdH5QI5QrhkRwlWr6T XJfNDF+8oUUIlNYeD9iSOiZt+W7cnaWrHoM4Oga3O610eS6f0hGmfVxlXUxUfT/4 3x/MKcSXI4SnwXuXrxmqmTm7sVCXP8cbqrIZzN5VUo341B1uqQ5bp1hRmiLt+cvY pnCk3MgYCuZAXRQrLShJkFeu3lJ/W89DVAY5v5+VAMR3jD/tTvQ5bP4HdBMJP4RY AyoI/4cmlAnvOq4Yr8wKdWo7/fgkj9sTHV11sRWkiOdKhLZe9aNYnv1Bd2COhmvH gJcWZ8SNpJ364iRoQPy1PeKxuSMQaesUKWXkvkqjsaGKD9gr2QjTpI3yN6wU3O5+ lT4wGsDMHDhpQml2r19+D3XGm5oA+t2sr1/27WjKBDYopTtZF/KuJ1xVMnIRxzJW M+V3BcM4RPivmv0a+ICA6f1WwE59EeBBzOfZ+VjBpnQAfTv9HRN1yCIVWRN8hIiz cC/iuY6tGxpdZf965fYCIj5cZ2OmCbIw1mh5hUSLDIaCd9+qXl7cgT7stpLar7kA tYDazF2J3v+XqUeyWtPndzAFdgr4rLNH9Q9kDKS9fyXOspIFqv6bBhAMMxiiTbT5 zj5Y2K1lAyHLTTwWmcNruw== =b/pm -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20230105' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Implement AArch32 ARMv8-R support * Add Cortex-R52 CPU * fix handling of HLT semihosting in system mode * hw/timer/ixm_epit: cleanup and fix bug in compare handling * target/arm: Coding style fixes * target/arm: Clean up includes * nseries: minor code cleanups * target/arm: align exposed ID registers with Linux * hw/arm/smmu-common: remove unnecessary inlines * i.MX7D: Handle GPT timers * i.MX7D: Connect IRQs to GPIO devices * i.MX6UL: Add a specific GPT timer instance * hw/net: Fix read of uninitialized memory in imx_fec # gpg: Signature made Thu 05 Jan 2023 16:43:18 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230105' of https://git.linaro.org/people/pmaydell/qemu-arm: (34 commits) hw/net: Fix read of uninitialized memory in imx_fec. i.MX7D: Connect IRQs to GPIO devices. i.MX6UL: Add a specific GPT timer instance for the i.MX6UL i.MX7D: Compute clock frequency for the fixed frequency clocks. i.MX7D: Connect GPT timers to IRQ hw/arm/smmu-common: Avoid using inlined functions with external linkage hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope target/arm: align exposed ID registers with Linux hw/arm/nseries: Silent -Wmissing-field-initializers warning hw/arm/nseries: Constify various read-only arrays hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg target/arm: cleanup cpu includes target/arm: Remove unused includes from helper.c target/arm: Remove unused includes from m_helper.c target/arm: Fix checkpatch brace errors in helper.c target/arm: Fix checkpatch space errors in helper.c target/arm: Fix checkpatch comment style warnings in helper.c hw/timer/imx_epit: fix compare timer handling hw/timer/imx_epit: remove explicit fields cnt and freq hw/timer/imx_epit: factor out register write handlers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Ilya Leoshkevich
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d4846c33eb |
tests/tcg/multiarch: add vma-pthread.c
Add a test that locklessly changes and exercises page protection bits from various threads. This helps catch race conditions in the VMA handling. Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221223120252.513319-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
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Marco Liebel
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d63aeb3b7e |
Hexagon (target/hexagon) implement mutability mask for GPRs
Some registers are defined to have immutable bits, this commit will implement that behavior. Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com> |
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Mukilan Thiyagarajan
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eaee3b6faf |
tests/tcg/hexagon: fix underspecifed asm constraints
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail. In misc.c, the 'result' output needs the early clobber modifier since the rest of the inputs are read after assignment to the output register. In mem_noshuf.c, the register r7 is written to but not specified in the clobber list. Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229081836.12130-1-quic_mthiyaga@quicinc.com> |
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Mukilan Thiyagarajan
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c979d901c8 |
linux-user/hexagon: fix signal context save & restore
This patch fixes the issue originally reported in this thread: https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html The root cause of the issue is a bug in the hexagon specific logic for saving & restoring context during signal delivery. The CPU state has two different representations for the predicate registers. The current logic saves & restores only the aliased HEX_REG_P3_O register, which is part of env->gpr[] field in the CPU state, but not the individual byte-level predicate registers (pO, p1, p2, p3) backed by env->pred[]. Since all predicated instructions refer only to the indiviual registers, switching to and back from a signal handler can clobber these registers if the signal handler writes to them causing the normal application code to behave unpredictably when context is restored. In the reported issue with the 'signals' test, since the updated hexagon toolchain had built musl with -O2, the functions called from non_trivial_free were inlined. This meant that the code emitted reused predicate P0 computed in the entry translation block of the function non_trivial_free in one of the child TB as part of an assertion. Since P0 is clobbered by the signal handler in the signals test, the assertion in non_trivial_free fails incorectly. Since musl for hexagon implements the 'abort' function by deliberately writing to memory via null pointer, this causes the test to fail with segmentation fault. This patch modifies the signal context save & restore logic to include the individual p0, p1, p2, p3 and excludes the 32b p3_0 register since its value is derived from the former registers. It also adds a new test case that reliabily reproduces the issue for all four predicate registers. Buglink: https://github.com/quic/toolchain_for_hexagon/issues/6 Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229092006.10709-2-quic_mthiyaga@quicinc.com> |