The functions softusb_read_pmem() and softusb_write_pmem() are unused;
remove them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The function tcg_gen_lshift() is unused; remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The function is_parallel_epp() is unused; remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The IRQ_testbit() function is never used; remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The stream_halted() function is never used; remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The 'on' variable is never used, and 'off' is only used
if IPV6_V6ONLY is defined; delete 'on' and move 'off' to
the point where it is used. This avoids warnings from
clang 3.4.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Drop the sd_acmd_type[] array: it is never used. (The equivalent
sd_cmd_type[] array for normal commands is used to identify
those commands whose argument includes the card address in the
top 16 bits; but for app commands the card address is passed
with the APP_CMD prefix, not with the argument to the app command
itself.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The variables parallel_io and parallel_irq are unused; delete them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The zero_ethaddr[] array is never used; delete it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Add a debug printf for TX descriptor fetching. This is helpful to anyone
needing to debug TX ring buffer traversal. It is also now consistent with
the RX code which has a similar printf.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The local variable "desc" was being used to read-modify-write the
first descriptor (of a multi-desc packet) upon packet completion.
desc however continues to be used by the code as the current
descriptor. Give this first desc RMW it's own local variable to
avoid trampling.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
- bugfixes: A fix for a long-standing bug in the css code as well as
a fixup for the recent I/O adapter support.
- Exploitation of the userspace cmma enablement/reset interface, if
it is present.
- Some debuggability improvements by logging unmanageable conditions.
- virtio-ccw finally gets migration support for its structures.
- Some cleanup as to how floating interrupts are injected.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJTlrqEAAoJEN7Pa5PG8C+v+C0P/iuCl+hMUosrTSry7Gww75S3
pdjr0Bs2b6Wsql8EOwaR4yj3DfNWoXOw9AYoESz7R2fn82TbONq+NHz+c/cUxCqB
B5aTSc/sSn6in4xSxSWuOMyQDu7yosRBPRqhgtxvWm0OEbWFBfC1A08C3tQY8EZm
Sis1JEYVKBQcI1jzT+JVuKEUWZK5aqidcTzN1LeDUHVL6tEEkmboEG1ZsxNsaYW5
YOhLXjH5N0of7Rqk+U2r5S9/ZC5SqxjipvEblc9eLKY1AmkP7kboL6R7kXYWmlND
QBq8pCCCr9kh5g6gTDylgBQhR2KAtyN+H9tueVBBY/hMBJOk4ZexLxrtp0QiItdg
eCeee/6sIJp2GtarwoPzZJnm0CbPmIWDmoOobmAfp/q6MA34sjlKD+VETuQk0iUp
7nHgecbNIuWN1Tm2hGJvVo8DtGyr9jEW0xURMTfb1sRyXzH/2eL93i7/VpHcIsMM
fwmI48vWSFrMDKGSBli/dgQe6TQkYfeM0z6pDWKfIKeaLWx+XZ2vgP4txfuSajVT
A09bXo83jnNZ9UhkyQtXAyNqHAx6De/blbrQw9nvMp+n9NFpQFxUSfHsNBDcVHso
lwfBT7RXatfgp5NpQp8rCNn6LLI2jbCLyxJoeosx+cgnKSQFCC76ijuFkNPPMUZk
DVakR1WqCEg9VFPQy8ug
=c2hc
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20140610' into staging
Several patches for s390:
- bugfixes: A fix for a long-standing bug in the css code as well as
a fixup for the recent I/O adapter support.
- Exploitation of the userspace cmma enablement/reset interface, if
it is present.
- Some debuggability improvements by logging unmanageable conditions.
- virtio-ccw finally gets migration support for its structures.
- Some cleanup as to how floating interrupts are injected.
# gpg: Signature made Tue 10 Jun 2014 08:57:56 BST using RSA key ID C6F02FAF
# gpg: Can't check signature: public key not found
* remotes/cohuck/tags/s390x-20140610:
s390x/kvm: inject via flic
s390x: cleanup interrupt injection
s390x/kvm: add alternative injection interface
s390x: consolidate floating interrupts
s390/virtio-ccw: migration support
s390x/kvm: Log unmanageable program interruptions
s390x/kvm: Log unmanageable external interruptions
s390x/kvm: enable/reset cmma via vm attributes
s390x/kvm: make flic play well with old kernels
s390x/css: handle emw correctly for tsch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Try to inject floating interrupts via the flic if it is available.
This allows us to inject the full range of floating interrupts.
Reviewed-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Remove the need for a cpu to inject a floating interrupt on kvm.
Acked-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Add kvm_s390_{vcpu,floating}_interrupt, which offer the possibility
to inject interrupts with larger payloads (when a kvm backend becomes
available).
Moreover, kvm_s390_floating_interrupt() does no longer have the bogus
requirement for a vcpu.
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Move the injection code for all floating interrupts to interrupt.c
and add a comment.
Also get rid of the #ifdef CONFIG_KVM for the service interrupt.
Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
This patch adds live migration support for virtio-ccw devices.
It's not done with vmstate because virtio itself is not yet ported
to vmstate either.
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
The kernel only drops to userspace if an endless program interrupt loop
has been detected. Let's print an error message in this case to inform
the user about the crash and stop the affected CPU with a panic event,
just like it is already done for the external interruption loop detection.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Interception code 0x14 only drops to userspace when an unmanageable
external interruption interception occured (e.g. if the External New
PSW does not disable external interruptions). Instead of bailing out
via the default handler, it is better to inform the user with a
proper error message that also includes the bad PSW, and to stop
the affected CPU with a panic event instead.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Exploit the new api for userspace-controlled cmma. If supported, enable
cmma during kvm initialization and register a reset handler for cmma,
which is also called directly from the load IPL code.
The reset functionality is needed to reset the cmma state of the guest
pages, e.g. if a system reset is triggered via qemu monitor; otherwise
this could result in data corruption.
A guest triggered reboot may now lead to multiple cmma resets; this is
OK, however, as this is slowpath anyway and the simplest way to achieve
the intended effects.
Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
If we run with an old kernel that does not support KVM_CAP_IRQ_ROUTING,
we don't have to do anything in the ->register_io_adapter and
->io_adapter_map callbacks and therefore should return 0 instead of
-ENOSYS (just as the non-kvm flic does).
This fixes using adapter interrupts when running under an older kernel,
which broke with "s390x: add I/O adapter registration".
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
We should not try to store the emw portion of the irb if extended
measurements are not applicable. In particular, we should not surprise
the guest by storing a larger irb if it did not enable extended
measurements.
Cc: qemu-stable@nongnu.org
Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Tested-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
target-arm queue:
* support -bios option in vexpress boards
* register the Cortex-A57 impdef system registers
* fix handling of UXN bit in ARMv8 page tables
* complete support of crypto insns in A32/T32
* implement CRC and crypto insns in A64
* fix bugs in generic timer control register
----------------------------------------------------------------
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABCAAGBQJTlc3qAAoJEDwlJe0UNgzeZYsP/18PXMyDjeP7yl/kFXJ3YJ/E
XdulZM3tYm7SA1PhgKKt3apCpL8lNhvlckjdbERT3+Pr4HaxOFEz1IkAu0fjrYOl
Vq1c3H5N4iLpfJMhNl/iB4JQ+9UgWv1THet0sfgAOFto1vGlUADRMLZVoZbPiPO8
+Zs0wKKyWoj1kKcZ7cVsp+hN+GDe5YtH3HM6io7ZzJWgSkVHgbkP4a7kYdkOSQUb
x88pfm7Xn4LuerupDFQLBuT3CVcpWbd8aOWp2BqUG913xFkK4lVstSIF7jLm4hnR
k/1Yiw/OFGCHmFIV8ABF2fw5YSB3iJ/RVKG01Rlac67Z9OzhySa4ssJ0JHjY+Wzd
L8mE5upUZZNvpUg1K5x7cy8/AYVlx8erWfteqGcmrYJqaAKek6+ySHiqf2ZsdZzk
C9OP3i/BHUlowP2P29VcWnj8R1a6pljXxqkIhu1GPkkZ09o1NWxEm7RxkLBij2Vp
sObuTJgg3rWnZ/DmGjDg3u1OwlRz+JRyadKwhPeZ5ZqESqqT3O+OOh8H76e/HG4F
Y5PXXEtPK0v/bttkvtv4GTJcNiHLtgYrF6+Mw+3xi7SNE15vvY1zop1csMLaLafT
DUf9rcbUPBKY/8kFXXWEUWm01mgB7t0MlrVK9AFwSEoYHc9xox5fpsKswwRXVQ+6
RH0wdjFMVCa58JQuqcOc
=bdN6
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140609-1' into staging
----------------------------------------------------------------
target-arm queue:
* support -bios option in vexpress boards
* register the Cortex-A57 impdef system registers
* fix handling of UXN bit in ARMv8 page tables
* complete support of crypto insns in A32/T32
* implement CRC and crypto insns in A64
* fix bugs in generic timer control register
----------------------------------------------------------------
# gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-20140609-1:
target-arm: Delete unused iwmmxt_msadb helper
target-arm: Fix errors in writes to generic timer control registers
target-arm: A64: Implement two-register SHA instructions
target-arm: A64: Implement 3-register SHA instructions
target-arm: A64: Implement AES instructions
target-arm: A32/T32: Mask CRC value in calling code, not helper
target-arm: A64: Implement CRC instructions
target-arm: VFPv4 implies half-precision extension
target-arm: Clean up handling of ARMv8 optional feature bits
target-arm: Remove unnecessary setting of feature bits
target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64
target-arm: A64: Use PMULL feature bit for PMULL
target-arm: add support for v8 VMULL.P64 instruction
target-arm: Allow 3reg_wide undefreq to encode more bad size options
target-arm: add support for v8 SHA1 and SHA256 instructions
target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
target-arm: Prepare cpreg writefns/readfns for EL3/SecExt
target-arm/cpu64.c: Actually register Cortex-A57 impdef registers
vexpress: Add support for the -bios flag to provide firmware
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJTlboyAAoJEJykq7OBq3PI+18IALIWg+SS+mCRRWIbFDPeTiJc
PRKleraINbruHTxJBmv/a5/xoZZEnAjXou1ZCtlAY+NlC4M4hOk4duAM5dad35QO
4XwLgQI9UV5K1ZbkkK8CwXF/W4wwCeDNFBDV+4xmnDnqBqYYOTPxVoxmFHkw8QZ+
fXWX0QPRNH++et+bMOo+IAmwiZ8Al0RLRULm7VDsRyXJmQpcOpdliyYu832ynN9G
thsGr03gz3gJzgui4bTYGn9yXP5QDsObsXJlDXZU7dzDKnz2XH4NB3vQCuyUyJWP
VVBbyffHyTIULk1WassdtkRLyfcHU394O7WbWtGiBb5qmodI/vORn/k1hjEhJfY=
=wCWL
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
Tracing pull request
# gpg: Signature made Mon 09 Jun 2014 14:44:18 BST using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
* remotes/stefanha/tags/tracing-pull-request:
trace: Replace fprintf with error_report and print location
trace: Multi-backend tracing
trace: Replace error with warning if event is not defined
simpletrace: add support for trace record pid field
trace: add pid field to simpletrace record
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The iwmmxt_msadb helper and its corresponding gen function are unused;
delete them. (This function appears to have never been used right back
to the initial implementation of iwMMXt; it is identical to iwmmxt_madduq,
and is presumably an accidental remnant from the initial development.)
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401822125-1822-1-git-send-email-peter.maydell@linaro.org
The code for handling writes to the generic timer control registers
had several bugs:
* ISTATUS (bit 2) is read-only but we forced it to zero on any write
* the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where
it should be '^'
* the handling of IMASK was inverted: we should set the IRQ if
ISTATUS is set and IMASK is clear, not if both are set
The combination of these bugs meant that when running a Linux guest
that uses the generic timers we would fairly quickly end up either
forgetting that the timer output should be asserted, or failing to
set the IRQ when the timer was unmasked. The result is that the guest
never gets any more timer interrupts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401803208-1281-1-git-send-email-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Bring the 32-bit CRC helper functions into line with the A64 ones,
by masking the high bytes of the value in the calling code rather
than the helper. This is more efficient since we can determine the
mask at translation time.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401458125-27977-7-git-send-email-peter.maydell@linaro.org
VFPv4 implies the presence of the half-precision floating point
extension (which is optional in VFPv3). Add this implied rule
to arm_cpu_realizefn() and remove some no-longer-needed explicit
setting of the bit in initfns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401458125-27977-5-git-send-email-peter.maydell@linaro.org
CRC and crypto are both optional v8 extensions, so FEATURE_V8
should not imply them. Instead we should set these bits in the
initfns for the 32-bit and 64-bit "cpu any" and for the Cortex-A57.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401458125-27977-4-git-send-email-peter.maydell@linaro.org
FEATURE_V8 implies both FEATURE_V7MP and FEATURE_ARM_DIV, so
we don't need to set them explicitly in initfns which set the
V8 feature bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401458125-27977-3-git-send-email-peter.maydell@linaro.org
The arm_any_initfn() is used only for the 32-bit linux-user "cpu any",
so it only gets called in builds where TARGET_AARCH64 is not defined.
Remove the unreachable line which sets ARM_FEATURE_AARCH64.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401458125-27977-2-git-send-email-peter.maydell@linaro.org
Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for
the A64 PMULL, not the AES feature bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add support for the VMULL.P64 polynomial 64x64 to 128 bit multiplication
instruction in the A32/T32 instruction sets; this is part of the v8
Crypto Extensions.
To do this we have to move the neon_pmull_64_{lo,hi} helpers from
helper-a64.c into neon_helper.c so they can be used by the AArch32
translator.
Inspired-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401386724-26529-4-git-send-email-peter.maydell@linaro.org
The current undefreq field in the neon_3reg_wide handling allows us
to encode "UNDEF if size != 0" and "UNDEF if size == 0". This is
no longer sufficient with the advent of 64-bit polynomial VMULL,
which means we want to UNDEF if size == 1. Change the undefreq
encoding to use separate bits for all of "UNDEF if size == 0",
"UNDEF if size == 1" and "UNDEF if size == 2".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401386724-26529-3-git-send-email-peter.maydell@linaro.org
This adds support for the SHA1 and SHA256 instructions that are available
on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401386724-26529-2-git-send-email-peter.maydell@linaro.org
[PMM:
* rebase
* fix bad indent
* add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case
* use g_assert_not_reached()
* don't re-extract bit 6 for the 2-reg-misc encodings
* set the ELF HWCAP2 bits for the new features
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes
and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we
can just treat this bit as UXN whenever we are in v8 mode.
Also correctly extract the upper attributes from the PTE entry, the v8 version
tried to avoid extracting the CONTIG bit and ended up with the upper bits being
off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG
bit.
This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f"
seen when modprobing modules under Linux.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Claudio Fontana <claudio.fontana@huawei.com>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This patch changes some readfns/writefns to use raw_write
and raw_read functions, which use the fieldoffset specified
in ARMCPRegInfo instead of directly accessing the field.
This will simplify patches for EL3 & Security Extensions.
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Message-id: 1401962428-14749-1-git-send-email-aggelerf@ethz.ch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
cpu64.c contains a reginfo list for the impdef registers on
the Cortex-A57; however we forgot to actually call define_arm_cp_regs(),
so it was sitting there doing nothing. Remedy this omission.
Message-id: 1401226259-23121-1-git-send-email-peter.maydell@linaro.org
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Right now to run firmware inside the QEMU VExpress model requires
padding out the firmware image to the size of the virtual flash and
passing it in via the -pflash argument. If the firmware image is passed
without padding, then QEMU will fail. Also, when passed as a -pflash
argument, QEMU treats the file as persistent storage and will modify the
file.
The -bios flag provides the semantics that we want for providing a
firmware image. This patch maps the contents of the -bios file into the
address space at the boot flash location.
Tested with the vexpress-a15 model and the Tianocore port.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Tested-by: Roy Franz <roy.franz@linaro.org>
[PMM: folded long line, removed stray \n from error message,
use correct variable for printing image name, exit(1) rather than 0]
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
