This patch adds the Vector Pack Doubleword instructions introduced in
Power ISA Version 2.07:
- Vector Pack Signed Doubleword Signed Saturate (vpksdss)
- Vector Pack Signed Doubleword Unsigned Saturate (vpksdus)
- Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum)
- Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Vector Minimum and Maximum Doubleword instructions
that are introduced in Power ISA Version 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Vector Population Count instructions introduced in Power
ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Vector Count Leading Zeroes instructions introduced
in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm)
instruction.
The existing VARITH_DO macro is re-used to (trivially) instantiate
the helper code.
Since bits 21-31 of any vmuluwm instruction is 137, the instruction
is coded as a dual to vmulouw (bits 21-31 = 136).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:
- Vector Multiply Even Unsigned Word (vmuleuw)
- Vector Multiply Even Signed Word (vmulesw)
- Vector Multiply Odd Unsigned Word (vmulouw)
- Vector Multiply Odd Signed Word (vmulosw)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This VMUL_DO macro provides support for the various vmule* and vmulo*
instructions. These instructions multiply vector elements, producing
products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit
elements and produces a 16 bit unsigned element.
The existing macro works correctly for the existing instructions (8-bit,
and 16-bit source elements) but does not work correctly for 32-bit
source elements.
This patch adds an explicit cast to the multiplicands, forcing them to be
of the target element type. This is required for the forthcoming patches
that add the vmul[eo][us]w instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds two Altivec unsigned doublword modulo instructions that
are introduced in Power ISA Version V2.07:
- vaddudm : Vector Add Unsigned Doubleword Modulo
- vsubudm : Vector Subtrace Unsigned Doubleword Modulo
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Vector Logical Instructions that are introduced
in Power ISA Version 2.07: veqv, vnand and vorc.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode but also use bit 21 as an actual Rc
bit. QEMU for PowerPC typically uses bits 0-5 and 21-30 for opcodes.
This patch introduces a generator macro that injects an auxiliary handler
which decodes both bits 21 and 31 and invokes one of four standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* flags are supported.
This patch also introduces a macro to insert two entries into the opcode
table -- one for bit 21 equal to 0 and one for bit 21 equal to 1.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a macro to insert an entry into the opcode table for Altivec
Power ISA Version 2.07 instructions. The macro is similar to the GEN_VXFORM macro
except that it tags the entry with the PPC2_ALTIVEC_207 flag rather than
PPC_ALTIVEC.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses
bits 0-5 and 21-30 for opcodes and not bit 31.
This patch introduces macros that will handle this situation by injecting
an auxiliary handler which decodes bit 31 in invokes one of two standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds generator macro for Altivec instructions that have 3
source AVR operands. The macro is similar to the 2 operand form.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch updates the ppc_avr_t data structure to include elements for
signed 64-bit integers and (conditionally) unsigned 128 bit integers.
These elements will be in instructions models later on in this patch series.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a flag that will be used to tag the Altivec instructions
introduced in Power ISA Version 2.07.
The flag is added to Power8 model since P8 supports these instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Store Quadword Conditionl (stqcx.) instruction
which is introduced in Power ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
[agraf: fix compile error when !TARGET_PPC64]
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Load Quadword and Reserve (lqarx) instruction,
which is new in Power ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds support for the Store Quadword instruction in user mode. Prior
to Power ISA 2.07, stq was legal only in privileged mode. Support for Little
Endian mode is also new in ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Book I (user space) Load Quadword (lq) instruction.
This instruction was introduced into Book I in Power ISA V2.07. Previous
versions of the architecture supported this as a privileged instruction.
Previous versions of the architecture also did not support Little Endian
mode.
Note that this patch also adds the PPC_64BX flag to the Power8 model,
which enables the lq instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a boolean function is_user_mode that can be re-used
in translation code that is sensitive to the MSR[PR] (user-mode)
state.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a flag to identify the load/store quadword instructions
that are introduced with Power ISA 2.07.
The flag is added to the Power8 model since P8 supports these
instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Branch Conditional to Address Register (bctar)
instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds support for the Target Address Register (TAR) to the Power8
model.
Because supported SPRs are typically identified in an init_proc_*()
function and because the Power8 model is currently just using the
init_proc_POWER7() function, a new init_proc_POWER8() function
is added and plugged into the P8 model.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a flag for the bctar instruction. This instruction
is being introduced via Power ISA 2.07.
Also, the flag is added to the Power8 machine model since the P8
processor supports this instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
The existing implementation of xxpermdi is defective if the target
VSR is also a source VSR. This patch fixes the defect in this case
but also preserves the simpler, two TCG operation implementation
when the target is not once of the two sources.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
PR KVM lacks support of many SPRs in set/get one register API but it does
really break PR KVM. So convert them to switchable traces for now.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
When ppc_store_slb() is called from kvm_arch_get_registers(), it stores
a SLB in CPUPPCState::slb[slot]. However it drops the slot number from
ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not
have correct "index" field anymore. This broke migration with LPCR_AIR
enabled as now the guest is handling interrupts in virtual mode and unable
to reconstruct correct SLBs anymore.
This adds "index" field for valid SLBs when putting them to KVM.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
The frsqrtes instruction was introduced prior to ISA 2.06 and is
support on both the Power7 and Power8 processors. However, this
instruction is handled as illegal in the current QEMU emulation
machines. This patch enables the existing implemention of frsqrtes
in the P7 and P8 machines.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.
Also, the existing helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06B. A common macro is provided to
eliminate repetitious code, and the existing fcfid instruction is
refactored to use this macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:
- Floating Convert to Integer Word Unsigned (fctiwu)
- Floating Convert to Integer Word Unsigned with Round Toward
Zero (fctiwuz)
- Floating Convert to Integer Doubleword Unsigned (fctidu)
- Floating Convert to Integer Doubleword Unsigned with Round
Toward Zero (fctiduz)
A common macro is developed to eliminate repetitious code. Existing instructions
are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a flag for the floating point conversion instructions
introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are refactored to use this macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the byte and halfword variants of the Load and
Reserve instructions. Since there is much commonality among
all forms of Load and Reserve, a macro is provided and the existing
implementations of lwarx and ldarx are refactoried to use this
macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch addes the signed Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch addes the Unsigned Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Divide Doubleword Extended Unsigned
instructions. This instruction requires dividing a 128-bit
value by a 64 bit value. Since 128 bit integer division is
not supported in TCG, a helper is used. An architecture
independent 128-bit division routine is added to host-utils.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[agraf: use ||]
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds a flag for the Divide Extended instructions that
were introduced in Power ISA V2.06B. The flag is added to the
Power7 and Power8 models.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the non-signalling scalar conversion instructions:
- VSX Scalar Convert Single Precision to Double Precision
Non-Signalling (xscvspdpn)
- VSX Scalar Convert Double Precision to Single Precision
Non-Signalling (xscvdpspn)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the VSX Scalar Round to Single Precision (xsrsp)
instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)
and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These
instructions are unusual in that they are considered a floating
point instruction if the indexed VSR is in the first half of the
array (0-31) but they are considered vector instructions if the
indexed VSR is in the second half of the array (32-63).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
