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223 Commits

Author SHA1 Message Date
edgar_igl
b52901b948 Remove unused members. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4070 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-16 16:38:48 +00:00
edgar_igl
3157a0a93b More TCG conversions for CRIS. 
* Bit swap insn (bitwise not, endian swap and bit reverse).
* Muls and mulu.
* Extended arithmetics.
* Parts of the condition code handling.
* Use tcg_const_tl.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4069 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-15 20:45:05 +00:00
edgar_igl
54728ac6db Simplified some dead extended arith code after search and replace. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4066 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-15 09:13:04 +00:00
edgar_igl
05ba7d5f34 A first small step to convert the CRIS translator to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4057 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-14 01:11:25 +00:00
edgar_igl
786c02f1ac Model more parts of the ETRAX mmu (still alot missing). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4056 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-14 01:08:09 +00:00
edgar_igl
e62b5b133b * Add a model of the ETRAX interrupt controller. 
* Clean up the interrupt handling a bit.
* Connect some NOR flash to the test board.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4055 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-14 01:04:24 +00:00
edgar_igl
bbaf29c769 * target-cris/op.c: Make sure the bit-test insn only updates the XNZ flags. 
* target-cris/helper.c: Update ERP for user-mode simulation aswell.
* hw/etraxfs_timer.c: Support multiple timers.
* hw/etraxfs_ser.c: Multiple ports, the data just goes to stdout.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4004 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-01 17:25:33 +00:00
edgar_igl
4f400ab520 Cut the translation block after translating a break insn. This avoids an issue where QEMU finds an illegal CRIS insn while the guest is returning through a signal return trampoline. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3997 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-28 09:37:58 +00:00
edgar_igl
9004627f9b More consistent naming for CRIS register-number macros. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3996 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-28 08:28:32 +00:00
edgar_igl
5d4a534dec Silently ignore CRIS cache flushes, instead of aborting due to unknown insn. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3990 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-25 09:58:22 +00:00
bellard
57fec1fee9 use the TCG code generator 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-01 10:50:11 +00:00
balrog
fd56059fb6 Optimize clear insns by treating support reg P0 specially and 
add missing micro-op RETURN's (Edgar E. Iglesias).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3913 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-01-14 03:18:30 +00:00
bellard
44f8625d23 fixed invalid type 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-11 12:35:55 +00:00
bellard
aaed909a49 added cpu_model parameter to cpu_init() 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-10 15:15:54 +00:00
ths
273af66025 Adjust s390 addresses (the MSB is defined as "to be ignored"). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-29 14:39:49 +00:00
ths
941db52871 Use the shiny new clz helpers. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3464 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-28 01:44:40 +00:00
j_mayer
6ebbf39000 Replace is_user variable with mmu_idx in softmmu core, 
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-14 07:07:08 +00:00
ths
94cff60a02 CRIS MMU emulation, by Edgar E. Iglesias. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3362 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-08 13:11:58 +00:00
ths
81fdc5f8d2 The remainder of CRIS CPU emulation files, by Edgar E. Iglesias. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3361 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-08 13:04:02 +00:00
ths
4fa551d768 CRIS micro-ops, by Edgar E. Iglesias. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3360 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-08 12:52:43 +00:00
ths
5478670f3d CRIS insn decoding macros, by Edgar E. Iglesias. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3359 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-08 12:50:59 +00:00
ths
8170028d75 CRIS instruction translation, by Edgar E. Iglesias. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3358 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-08 12:49:08 +00:00
ths
450d4ff553 CRIS disassembler, originally from binutils, by Edgar E. Iglesias. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3356 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-08 12:45:38 +00:00