mirror of https://gitlab.com/qemu-project/qemu
target-alpha: Expand msk*h inline.
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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14ab163429
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@ -19,11 +19,8 @@ DEF_HELPER_1(cttz, i64, i64)
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DEF_HELPER_2(zap, i64, i64, i64)
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DEF_HELPER_2(zapnot, i64, i64, i64)
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DEF_HELPER_2(mskwh, i64, i64, i64)
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DEF_HELPER_2(inswh, i64, i64, i64)
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DEF_HELPER_2(msklh, i64, i64, i64)
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DEF_HELPER_2(inslh, i64, i64, i64)
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DEF_HELPER_2(mskqh, i64, i64, i64)
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DEF_HELPER_2(insqh, i64, i64, i64)
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DEF_HELPER_2(cmpbge, i64, i64, i64)
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@ -185,33 +185,18 @@ uint64_t helper_zapnot(uint64_t val, uint64_t mask)
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return byte_zap(val, ~mask);
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}
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uint64_t helper_mskwh(uint64_t val, uint64_t mask)
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{
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return byte_zap(val, (0x03 << (mask & 7)) >> 8);
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}
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uint64_t helper_inswh(uint64_t val, uint64_t mask)
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{
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val >>= 64 - ((mask & 7) * 8);
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return byte_zap(val, ~((0x03 << (mask & 7)) >> 8));
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}
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uint64_t helper_msklh(uint64_t val, uint64_t mask)
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{
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return byte_zap(val, (0x0F << (mask & 7)) >> 8);
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}
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uint64_t helper_inslh(uint64_t val, uint64_t mask)
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{
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val >>= 64 - ((mask & 7) * 8);
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return byte_zap(val, ~((0x0F << (mask & 7)) >> 8));
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}
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uint64_t helper_mskqh(uint64_t val, uint64_t mask)
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{
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return byte_zap(val, (0xFF << (mask & 7)) >> 8);
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}
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uint64_t helper_insqh(uint64_t val, uint64_t mask)
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{
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val >>= 64 - ((mask & 7) * 8);
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@ -579,8 +579,8 @@ static inline void gen_zap(int ra, int rb, int rc, int islit, uint8_t lit)
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/* EXTWH, EXTLH, EXTQH */
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static inline void gen_ext_h(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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static void gen_ext_h(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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{
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if (unlikely(rc == 31))
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return;
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@ -604,8 +604,8 @@ static inline void gen_ext_h(int ra, int rb, int rc, int islit,
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}
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/* EXTBL, EXTWL, EXTLL, EXTQL */
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static inline void gen_ext_l(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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static void gen_ext_l(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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{
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if (unlikely(rc == 31))
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return;
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@ -626,8 +626,8 @@ static inline void gen_ext_l(int ra, int rb, int rc, int islit,
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}
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/* INSBL, INSWL, INSLL, INSQL */
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static inline void gen_ins_l(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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static void gen_ins_l(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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{
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if (unlikely(rc == 31))
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return;
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@ -655,9 +655,47 @@ static inline void gen_ins_l(int ra, int rb, int rc, int islit,
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}
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}
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/* MSKWH, MSKLH, MSKQH */
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static void gen_msk_h(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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{
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if (unlikely(rc == 31))
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return;
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else if (unlikely(ra == 31))
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tcg_gen_movi_i64(cpu_ir[rc], 0);
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else if (islit) {
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gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~((byte_mask << (lit & 7)) >> 8));
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} else {
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TCGv shift = tcg_temp_new();
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TCGv mask = tcg_temp_new();
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/* The instruction description is as above, where the byte_mask
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is shifted left, and then we extract bits <15:8>. This can be
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emulated with a right-shift on the expanded byte mask. This
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requires extra care because for an input <2:0> == 0 we need a
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shift of 64 bits in order to generate a zero. This is done by
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splitting the shift into two parts, the variable shift - 1
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followed by a constant 1 shift. The code we expand below is
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equivalent to ~((B & 7) * 8) & 63. */
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tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
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tcg_gen_shli_i64(shift, shift, 3);
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tcg_gen_not_i64(shift, shift);
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tcg_gen_andi_i64(shift, shift, 0x3f);
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tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));
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tcg_gen_shr_i64(mask, mask, shift);
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tcg_gen_shri_i64(mask, mask, 1);
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tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);
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tcg_temp_free(mask);
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tcg_temp_free(shift);
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}
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}
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/* MSKBL, MSKWL, MSKLL, MSKQL */
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static inline void gen_msk_l(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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static void gen_msk_l(int ra, int rb, int rc, int islit,
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uint8_t lit, uint8_t byte_mask)
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{
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if (unlikely(rc == 31))
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return;
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@ -712,11 +750,8 @@ ARITH3(addlv)
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ARITH3(sublv)
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ARITH3(addqv)
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ARITH3(subqv)
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ARITH3(mskwh)
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ARITH3(inswh)
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ARITH3(msklh)
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ARITH3(inslh)
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ARITH3(mskqh)
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ARITH3(insqh)
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ARITH3(umulh)
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ARITH3(mullv)
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@ -1440,7 +1475,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
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break;
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case 0x52:
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/* MSKWH */
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gen_mskwh(ra, rb, rc, islit, lit);
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gen_msk_h(ra, rb, rc, islit, lit, 0x03);
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break;
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case 0x57:
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/* INSWH */
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@ -1452,7 +1487,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
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break;
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case 0x62:
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/* MSKLH */
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gen_msklh(ra, rb, rc, islit, lit);
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gen_msk_h(ra, rb, rc, islit, lit, 0x0f);
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break;
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case 0x67:
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/* INSLH */
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@ -1464,7 +1499,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
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break;
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case 0x72:
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/* MSKQH */
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gen_mskqh(ra, rb, rc, islit, lit);
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gen_msk_h(ra, rb, rc, islit, lit, 0xff);
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break;
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case 0x77:
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/* INSQH */
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