hw/acpi/aml-build: Make enum values to be upper case to match coding style
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-2-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Shannon Zhao
Peter Maydell
parent
b1eced713d
commit
ff80dc7fa8
@ -833,7 +833,7 @@ Aml *aml_word_bus_number(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
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uint16_t addr_trans, uint16_t len)
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{
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return aml_word_as_desc(aml_bus_number_range, min_fixed, max_fixed, dec,
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return aml_word_as_desc(AML_BUS_NUMBER_RANGE, min_fixed, max_fixed, dec,
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addr_gran, addr_min, addr_max, addr_trans, len, 0);
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}
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@ -850,7 +850,7 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
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uint16_t len)
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{
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return aml_word_as_desc(aml_io_range, min_fixed, max_fixed, dec,
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return aml_word_as_desc(AML_IO_RANGE, min_fixed, max_fixed, dec,
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addr_gran, addr_min, addr_max, addr_trans, len,
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isa_ranges);
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}
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@ -862,7 +862,7 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
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* ACPI 5.0: 19.5.34 DWordMemory (DWord Memory Resource Descriptor Macro)
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*/
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Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
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AmlMaxFixed max_fixed, AmlCacheble cacheable,
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AmlMaxFixed max_fixed, AmlCacheable cacheable,
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AmlReadAndWrite read_and_write,
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uint32_t addr_gran, uint32_t addr_min,
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uint32_t addr_max, uint32_t addr_trans,
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@ -870,7 +870,7 @@ Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
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{
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uint8_t flags = read_and_write | (cacheable << 1);
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return aml_dword_as_desc(aml_memory_range, min_fixed, max_fixed,
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return aml_dword_as_desc(AML_MEMORY_RANGE, min_fixed, max_fixed,
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dec, addr_gran, addr_min, addr_max,
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addr_trans, len, flags);
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}
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@ -882,7 +882,7 @@ Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
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* ACPI 5.0: 19.5.102 QWordMemory (QWord Memory Resource Descriptor Macro)
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*/
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Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
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AmlMaxFixed max_fixed, AmlCacheble cacheable,
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AmlMaxFixed max_fixed, AmlCacheable cacheable,
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AmlReadAndWrite read_and_write,
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uint64_t addr_gran, uint64_t addr_min,
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uint64_t addr_max, uint64_t addr_trans,
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@ -890,7 +890,7 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
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{
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uint8_t flags = read_and_write | (cacheable << 1);
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return aml_qword_as_desc(aml_memory_range, min_fixed, max_fixed,
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return aml_qword_as_desc(AML_MEMORY_RANGE, min_fixed, max_fixed,
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dec, addr_gran, addr_min, addr_max,
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addr_trans, len, flags);
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}
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@ -620,31 +620,31 @@ build_ssdt(GArray *table_data, GArray *linker,
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/* build PCI0._CRS */
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crs = aml_resource_template();
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aml_append(crs,
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aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
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aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08));
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aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
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AML_POS_DECODE, AML_ENTIRE_RANGE,
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0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
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AML_POS_DECODE, AML_ENTIRE_RANGE,
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0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
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aml_append(crs,
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aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
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aml_cacheable, aml_ReadWrite,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_CACHEABLE, AML_READ_WRITE,
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0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
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aml_append(crs,
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aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
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aml_non_cacheable, aml_ReadWrite,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE,
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0, pci->w32.begin, pci->w32.end - 1, 0,
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pci->w32.end - pci->w32.begin));
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if (pci->w64.begin) {
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aml_append(crs,
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aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
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aml_cacheable, aml_ReadWrite,
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_CACHEABLE, AML_READ_WRITE,
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0, pci->w64.begin, pci->w64.end - 1, 0,
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pci->w64.end - pci->w64.begin));
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}
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@ -658,7 +658,7 @@ build_ssdt(GArray *table_data, GArray *linker,
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aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
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aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
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);
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(scope, dev);
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@ -673,7 +673,7 @@ build_ssdt(GArray *table_data, GArray *linker,
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aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
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aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
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pm->pcihp_io_len)
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);
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aml_append(dev, aml_name_decl("_CRS", crs));
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@ -720,7 +720,7 @@ build_ssdt(GArray *table_data, GArray *linker,
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(aml_decode16, misc->applesmc_io_base, misc->applesmc_io_base,
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aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
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0x01, APPLESMC_MAX_DATA_LENGTH)
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);
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aml_append(crs, aml_irq_no_flags(6));
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@ -738,13 +738,13 @@ build_ssdt(GArray *table_data, GArray *linker,
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
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aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
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);
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(dev, aml_operation_region("PEOR", aml_system_io,
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aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
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misc->pvpanic_port, 1));
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field = aml_field("PEOR", aml_byte_acc, aml_preserve);
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field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE);
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aml_append(field, aml_named_field("PEPT", 8));
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aml_append(dev, field);
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@ -773,15 +773,15 @@ build_ssdt(GArray *table_data, GArray *linker,
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aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
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aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
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pm->cpu_hp_io_len)
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);
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(sb_scope, dev);
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/* declare CPU hotplug MMIO region and PRS field to access it */
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aml_append(sb_scope, aml_operation_region(
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"PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
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field = aml_field("PRST", aml_byte_acc, aml_preserve);
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"PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
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field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE);
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aml_append(field, aml_named_field("PRS", 256));
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aml_append(sb_scope, field);
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@ -845,18 +845,18 @@ build_ssdt(GArray *table_data, GArray *linker,
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
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aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
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pm->mem_hp_io_len)
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);
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aml_append(scope, aml_name_decl("_CRS", crs));
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aml_append(scope, aml_operation_region(
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stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io,
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stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO,
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pm->mem_hp_io_base, pm->mem_hp_io_len)
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);
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field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc,
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aml_preserve);
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field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
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AML_PRESERVE);
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aml_append(field, /* read only */
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aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
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aml_append(field, /* read only */
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@ -869,8 +869,8 @@ build_ssdt(GArray *table_data, GArray *linker,
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aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
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aml_append(scope, field);
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field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc,
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aml_write_as_zeros);
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field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC,
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AML_WRITE_AS_ZEROS);
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aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
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aml_append(field, /* 1 if enabled, read only */
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aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
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@ -885,8 +885,8 @@ build_ssdt(GArray *table_data, GArray *linker,
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aml_named_field(stringify(MEMORY_SLOT_EJECT), 1));
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aml_append(scope, field);
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field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc,
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aml_preserve);
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field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
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AML_PRESERVE);
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aml_append(field, /* DIMM selector, write only */
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aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
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aml_append(field, /* _OST event code, write only */
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@ -36,49 +36,49 @@ struct Aml {
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typedef struct Aml Aml;
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typedef enum {
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aml_decode10 = 0,
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aml_decode16 = 1,
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AML_DECODE10 = 0,
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AML_DECODE16 = 1,
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} AmlIODecode;
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typedef enum {
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aml_any_acc = 0,
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aml_byte_acc = 1,
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aml_word_acc = 2,
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aml_dword_acc = 3,
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aml_qword_acc = 4,
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aml_buffer_acc = 5,
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AML_ANY_ACC = 0,
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AML_BYTE_ACC = 1,
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AML_WORD_ACC = 2,
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AML_DWORD_ACC = 3,
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AML_QWORD_ACC = 4,
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AML_BUFFER_ACC = 5,
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} AmlAccessType;
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typedef enum {
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aml_preserve = 0,
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aml_write_as_ones = 1,
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aml_write_as_zeros = 2,
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AML_PRESERVE = 0,
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AML_WRITE_AS_ONES = 1,
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AML_WRITE_AS_ZEROS = 2,
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} AmlUpdateRule;
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typedef enum {
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aml_system_memory = 0x00,
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aml_system_io = 0x01,
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AML_SYSTEM_MEMORY = 0X00,
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AML_SYSTEM_IO = 0X01,
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} AmlRegionSpace;
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typedef enum {
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aml_memory_range = 0,
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aml_io_range = 1,
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aml_bus_number_range = 2,
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AML_MEMORY_RANGE = 0,
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AML_IO_RANGE = 1,
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AML_BUS_NUMBER_RANGE = 2,
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} AmlResourceType;
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typedef enum {
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aml_sub_decode = 1 << 1,
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aml_pos_decode = 0
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AML_SUB_DECODE = 1 << 1,
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AML_POS_DECODE = 0
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} AmlDecode;
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typedef enum {
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aml_max_fixed = 1 << 3,
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aml_max_not_fixed = 0,
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AML_MAX_FIXED = 1 << 3,
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AML_MAX_NOT_FIXED = 0,
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} AmlMaxFixed;
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typedef enum {
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aml_min_fixed = 1 << 2,
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aml_min_not_fixed = 0
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AML_MIN_FIXED = 1 << 2,
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AML_MIN_NOT_FIXED = 0
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} AmlMinFixed;
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/*
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@ -86,9 +86,9 @@ typedef enum {
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* _RNG field definition
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*/
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typedef enum {
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aml_isa_only = 1,
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aml_non_isa_only = 2,
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aml_entire_range = 3,
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AML_ISA_ONLY = 1,
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AML_NON_ISA_ONLY = 2,
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AML_ENTIRE_RANGE = 3,
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} AmlISARanges;
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/*
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@ -96,19 +96,19 @@ typedef enum {
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* _MEM field definition
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*/
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typedef enum {
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aml_non_cacheable = 0,
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aml_cacheable = 1,
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aml_write_combining = 2,
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aml_prefetchable = 3,
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} AmlCacheble;
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AML_NON_CACHEABLE = 0,
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AML_CACHEABLE = 1,
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AML_WRITE_COMBINING = 2,
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AML_PREFETCHABLE = 3,
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} AmlCacheable;
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/*
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* ACPI 1.0b: Table 6-25 Memory Resource Flag (Resource Type = 0) Definitions
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* _RW field definition
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*/
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typedef enum {
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aml_ReadOnly = 0,
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aml_ReadWrite = 1,
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AML_READ_ONLY = 0,
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AML_READ_WRITE = 1,
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} AmlReadAndWrite;
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typedef
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@ -191,13 +191,13 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
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uint16_t addr_max, uint16_t addr_trans,
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uint16_t len);
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Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
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AmlMaxFixed max_fixed, AmlCacheble cacheable,
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AmlMaxFixed max_fixed, AmlCacheable cacheable,
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AmlReadAndWrite read_and_write,
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uint32_t addr_gran, uint32_t addr_min,
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uint32_t addr_max, uint32_t addr_trans,
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uint32_t len);
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Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
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AmlMaxFixed max_fixed, AmlCacheble cacheable,
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AmlMaxFixed max_fixed, AmlCacheable cacheable,
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AmlReadAndWrite read_and_write,
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uint64_t addr_gran, uint64_t addr_min,
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uint64_t addr_max, uint64_t addr_trans,
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