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vt82c686: Convert debug printf to trace points

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Drop DPRINTF and use trace functions instead. Two debug messages about
unimplemented registers could be converted to qemu_log_mask() but in
reality all registers are currently unimplemented (we just store and
return values of writable regs but do nothing with them). As we
already trace register access there's no need for additional debug
messages so these are just removed and a comment is added as a reminder.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <785854022a37035f66d89e70cb6ca1bc0e0d0163.1609584216.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan 2021-01-02 11:43:35 +01:00 committed by Philippe Mathieu-Daudé
parent dc66439542
commit ff413a1f7f
2 changed files with 21 additions and 36 deletions
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6
hw/isa/trace-events
View File

@ -13,3 +13,9 @@ pc87312_io_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
# apm.c # apm.c
apm_io_read(uint8_t addr, uint8_t val) "read addr=0x%x val=0x%02x" apm_io_read(uint8_t addr, uint8_t val) "read addr=0x%x val=0x%02x"
apm_io_write(uint8_t addr, uint8_t val) "write addr=0x%x val=0x%02x" apm_io_write(uint8_t addr, uint8_t val) "write addr=0x%x val=0x%02x"
# vt82c686.c
via_isa_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len 0x%x"
via_pm_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len 0x%x"
via_superio_read(uint8_t addr, uint8_t val) "addr 0x%x val 0x%x"
via_superio_write(uint8_t addr, uint32_t val) "addr 0x%x val 0x%x"

51
hw/isa/vt82c686.c
View File

@ -27,14 +27,7 @@
#include "qemu/timer.h" #include "qemu/timer.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "qom/object.h" #include "qom/object.h"
#include "trace.h"
/* #define DEBUG_VT82C686B */
#ifdef DEBUG_VT82C686B
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
#else
#define DPRINTF(fmt, ...)
#endif
typedef struct SuperIOConfig { typedef struct SuperIOConfig {
uint8_t config[0x100]; uint8_t config[0x100];
@ -55,12 +48,12 @@ static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
{ {
SuperIOConfig *superio_conf = opaque; SuperIOConfig *superio_conf = opaque;
DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); if (addr == 0x3f0) { /* config index register */
if (addr == 0x3f0) {
superio_conf->index = data & 0xff; superio_conf->index = data & 0xff;
} else { } else {
bool can_write = true; bool can_write = true;
/* 0x3f1 */ /* 0x3f1, config data register */
trace_via_superio_write(superio_conf->index, data & 0xff);
switch (superio_conf->index) { switch (superio_conf->index) {
case 0x00 ... 0xdf: case 0x00 ... 0xdf:
case 0xe4: case 0xe4:
@ -73,18 +66,7 @@ static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
case 0xfd ... 0xff: case 0xfd ... 0xff:
can_write = false; can_write = false;
break; break;
case 0xe7: /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
if ((data & 0xff) != 0xfe) {
DPRINTF("change uart 1 base. unsupported yet\n");
can_write = false;
}
break;
case 0xe8:
if ((data & 0xff) != 0xbe) {
DPRINTF("change uart 2 base. unsupported yet\n");
can_write = false;
}
break;
default: default:
break; break;
@ -98,9 +80,10 @@ static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
{ {
SuperIOConfig *superio_conf = opaque; SuperIOConfig *superio_conf = opaque;
uint8_t val = superio_conf->config[superio_conf->index];
DPRINTF("superio_ioport_readb address 0x%x\n", addr); trace_via_superio_read(superio_conf->index, val);
return superio_conf->config[superio_conf->index]; return val;
} }
static const MemoryRegionOps superio_ops = { static const MemoryRegionOps superio_ops = {
@ -141,16 +124,14 @@ static void vt82c686b_isa_reset(DeviceState *dev)
} }
/* write config pci function0 registers. PCI-ISA bridge */ /* write config pci function0 registers. PCI-ISA bridge */
static void vt82c686b_write_config(PCIDevice *d, uint32_t address, static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
uint32_t val, int len) uint32_t val, int len)
{ {
VT82C686BISAState *vt686 = VT82C686B_ISA(d); VT82C686BISAState *vt686 = VT82C686B_ISA(d);
DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", trace_via_isa_write(addr, val, len);
address, val, len); pci_default_write_config(d, addr, val, len);
if (addr == 0x85) { /* enable or disable super IO configure */
pci_default_write_config(d, address, val, len);
if (address == 0x85) { /* enable or disable super IO configure */
memory_region_set_enabled(&vt686->superio, val & 0x2); memory_region_set_enabled(&vt686->superio, val & 0x2);
} }
} }
@ -203,12 +184,10 @@ static void pm_io_space_update(VT686PMState *s)
memory_region_transaction_commit(); memory_region_transaction_commit();
} }
static void pm_write_config(PCIDevice *d, static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
uint32_t address, uint32_t val, int len)
{ {
DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", trace_via_pm_write(addr, val, len);
address, val, len); pci_default_write_config(d, addr, val, len);
pci_default_write_config(d, address, val, len);
} }
static int vmstate_acpi_post_load(void *opaque, int version_id) static int vmstate_acpi_post_load(void *opaque, int version_id)