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Misc HW patch queue

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- Rename hw/ide/ahci-internal.h for consistency (Zoltan)
 - More convenient PCI hotplug trace events (Vladimir)
 - Short CLI option to add drives for sam460ex machine (Zoltan)
 - More missing ERRP_GUARD() macros (Zhao)
 - Avoid faulting when unmapped I/O BAR is accessed on SPARC EBUS (Mark)
 - Remove unused includes in hw/core/ (Zhao)
 - New PCF8574 GPIO over I2C model (Dmitriy)
 - Require ObjC on Darwin macOS by default (Peter)
 - Corrected "-smp parameter=1" placement in docs/ (Zhao)
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Merge tag 'hw-misc-20240312' of https://github.com/philmd/qemu into staging

Misc HW patch queue

- Rename hw/ide/ahci-internal.h for consistency (Zoltan)
- More convenient PCI hotplug trace events (Vladimir)
- Short CLI option to add drives for sam460ex machine (Zoltan)
- More missing ERRP_GUARD() macros (Zhao)
- Avoid faulting when unmapped I/O BAR is accessed on SPARC EBUS (Mark)
- Remove unused includes in hw/core/ (Zhao)
- New PCF8574 GPIO over I2C model (Dmitriy)
- Require ObjC on Darwin macOS by default (Peter)
- Corrected "-smp parameter=1" placement in docs/ (Zhao)

# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 12 Mar 2024 08:21:45 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20240312' of https://github.com/philmd/qemu:
  docs/about/deprecated.rst: Move SMP configurations item to system emulator section
  meson.build: Always require an objc compiler on macos hosts
  hw/gpio: introduce pcf8574 driver
  hw/core: Cleanup unused included headers in numa.c
  hw/core: Cleanup unused included header in machine-qmp-cmds.c
  hw/core: Cleanup unused included headers in cpu-common.c
  sun4u: remap ebus BAR0 to use unassigned_io_ops instead of alias to PCI IO space
  hw/misc/ivshmem: Fix missing ERRP_GUARD() for error_prepend()
  hw/core/qdev-properties-system: Fix missing ERRP_GUARD() for error_prepend()
  hw/core/loader-fit: Fix missing ERRP_GUARD() for error_prepend()
  hw/ppc/sam460ex: Support short options for adding drives
  hw/pci: add some convenient trace-events for pcie and shpc hotplug
  hw/ide/ahci: Rename ahci_internal.h to ahci-internal.h

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-03-12 13:42:49 +00:00
commit fe6d4434d2
21 changed files with 339 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -2503,6 +2503,12 @@ S: Maintained
F: hw/i2c/i2c_mux_pca954x.c
F: include/hw/i2c/i2c_mux_pca954x.h
pcf8574
M: Dmitrii Sharikhin <d.sharikhin@yadro.com>
S: Maintained
F: hw/gpio/pcf8574.c
F: include/gpio/pcf8574.h
Generic Loader
M: Alistair Francis <alistair@alistair23.me>
S: Maintained

20
docs/about/deprecated.rst
View File

@ -47,16 +47,6 @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
However, short-form booleans are deprecated and full explicit ``arg_name=on``
form is preferred.
User-mode emulator command line arguments
-----------------------------------------
``-p`` (since 9.0)
''''''''''''''''''
The ``-p`` option pretends to control the host page size. However,
it is not possible to change the host page size, and using the
option only causes failures.
``-smp`` (Unsupported "parameter=1" SMP configurations) (since 9.0)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
@ -71,6 +61,16 @@ configurations (e.g. -smp drawers=1,books=1,clusters=1 for x86 PC machine) is
marked deprecated since 9.0, users have to ensure that all the topology members
described with -smp are supported by the target machine.
User-mode emulator command line arguments
-----------------------------------------
``-p`` (since 9.0)
''''''''''''''''''
The ``-p`` option pretends to control the host page size. However,
it is not possible to change the host page size, and using the
option only causes failures.
QEMU Machine Protocol (QMP) commands
------------------------------------

4
hw/core/cpu-common.c
View File

@ -22,14 +22,10 @@
#include "qapi/error.h"
#include "hw/core/cpu.h"
#include "sysemu/hw_accel.h"
#include "qemu/notify.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "exec/log.h"
#include "exec/cpu-common.h"
#include "exec/gdbstub.h"
#include "qemu/error-report.h"
#include "qemu/qemu-print.h"
#include "sysemu/tcg.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"

2
hw/core/loader-fit.c
View File

@ -120,6 +120,7 @@ static int fit_load_kernel(const struct fit_loader *ldr, const void *itb,
int cfg, void *opaque, hwaddr *pend,
Error **errp)
{
ERRP_GUARD();
const char *name;
const void *data;
const void *load_data;
@ -178,6 +179,7 @@ static int fit_load_fdt(const struct fit_loader *ldr, const void *itb,
int cfg, void *opaque, const void *match_data,
hwaddr kernel_end, Error **errp)
{
ERRP_GUARD();
Error *err = NULL;
const char *name;
const void *data;

1
hw/core/machine-qmp-cmds.c
View File

@ -19,7 +19,6 @@
#include "qapi/qmp/qobject.h"
#include "qapi/qobject-input-visitor.h"
#include "qapi/type-helpers.h"
#include "qemu/main-loop.h"
#include "qemu/uuid.h"
#include "qom/qom-qobject.h"
#include "sysemu/hostmem.h"

2
hw/core/numa.c
View File

@ -28,7 +28,6 @@
#include "sysemu/numa.h"
#include "exec/cpu-common.h"
#include "exec/ramlist.h"
#include "qemu/bitmap.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qapi/opts-visitor.h"
@ -36,7 +35,6 @@
#include "sysemu/qtest.h"
#include "hw/core/cpu.h"
#include "hw/mem/pc-dimm.h"
#include "migration/vmstate.h"
#include "hw/boards.h"
#include "hw/mem/memory-device.h"
#include "qemu/option.h"

1
hw/core/qdev-properties-system.c
View File

@ -242,6 +242,7 @@ static void get_chr(Object *obj, Visitor *v, const char *name, void *opaque,
static void set_chr(Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp)
{
ERRP_GUARD();
Property *prop = opaque;
CharBackend *be = object_field_prop_ptr(obj, prop);
Chardev *s;

4
hw/gpio/Kconfig
View File

@ -19,3 +19,7 @@ config SIFIVE_GPIO
config STM32L4X5_GPIO
bool
config PCF8574
bool
depends on I2C

1
hw/gpio/meson.build
View File

@ -16,3 +16,4 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(
system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c'))

162
hw/gpio/pcf8574.c Normal file
View File

@ -0,0 +1,162 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* NXP PCF8574 8-port I2C GPIO expansion chip.
* Copyright (c) 2024 KNS Group (YADRO).
* Written by Dmitrii Sharikhin <d.sharikhin@yadro.com>
*/
#include "qemu/osdep.h"
#include "hw/i2c/i2c.h"
#include "hw/gpio/pcf8574.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qom/object.h"
/*
* PCF8574 and compatible chips incorporate quasi-bidirectional
* IO. Electrically it means that device sustain pull-up to line
* unless IO port is configured as output _and_ driven low.
*
* IO access is implemented as simple I2C single-byte read
* or write operation. So, to configure line to input user write 1
* to corresponding bit. To configure line to output and drive it low
* user write 0 to corresponding bit.
*
* In essence, user can think of quasi-bidirectional IO as
* open-drain line, except presence of builtin rising edge acceleration
* embedded in PCF8574 IC
*
* PCF8574 has interrupt request line, which is being pulled down when
* port line state differs from last read. Port read operation clears
* state and INT line returns to high state via pullup.
*/
OBJECT_DECLARE_SIMPLE_TYPE(PCF8574State, PCF8574)
#define PORTS_COUNT (8)
struct PCF8574State {
I2CSlave parent_obj;
uint8_t lastrq; /* Last requested state. If changed - assert irq */
uint8_t input; /* external electrical line state */
uint8_t output; /* Pull-up (1) or drive low (0) on bit */
qemu_irq handler[PORTS_COUNT];
qemu_irq intrq; /* External irq request */
};
static void pcf8574_reset(DeviceState *dev)
{
PCF8574State *s = PCF8574(dev);
s->lastrq = MAKE_64BIT_MASK(0, PORTS_COUNT);
s->input = MAKE_64BIT_MASK(0, PORTS_COUNT);
s->output = MAKE_64BIT_MASK(0, PORTS_COUNT);
}
static inline uint8_t pcf8574_line_state(PCF8574State *s)
{
/* we driving line low or external circuit does that */
return s->input & s->output;
}
static uint8_t pcf8574_rx(I2CSlave *i2c)
{
PCF8574State *s = PCF8574(i2c);
uint8_t linestate = pcf8574_line_state(s);
if (s->lastrq != linestate) {
s->lastrq = linestate;
if (s->intrq) {
qemu_set_irq(s->intrq, 1);
}
}
return linestate;
}
static int pcf8574_tx(I2CSlave *i2c, uint8_t data)
{
PCF8574State *s = PCF8574(i2c);
uint8_t prev;
uint8_t diff;
uint8_t actual;
int line = 0;
prev = pcf8574_line_state(s);
s->output = data;
actual = pcf8574_line_state(s);
for (diff = (actual ^ prev); diff; diff &= ~(1 << line)) {
line = ctz32(diff);
if (s->handler[line]) {
qemu_set_irq(s->handler[line], (actual >> line) & 1);
}
}
if (s->intrq) {
qemu_set_irq(s->intrq, actual == s->lastrq);
}
return 0;
}
static const VMStateDescription vmstate_pcf8574 = {
.name = "pcf8574",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_I2C_SLAVE(parent_obj, PCF8574State),
VMSTATE_UINT8(lastrq, PCF8574State),
VMSTATE_UINT8(input, PCF8574State),
VMSTATE_UINT8(output, PCF8574State),
VMSTATE_END_OF_LIST()
}
};
static void pcf8574_gpio_set(void *opaque, int line, int level)
{
PCF8574State *s = (PCF8574State *) opaque;
assert(line >= 0 && line < ARRAY_SIZE(s->handler));
if (level) {
s->input |= (1 << line);
} else {
s->input &= ~(1 << line);
}
if (pcf8574_line_state(s) != s->lastrq && s->intrq) {
qemu_set_irq(s->intrq, 0);
}
}
static void pcf8574_realize(DeviceState *dev, Error **errp)
{
PCF8574State *s = PCF8574(dev);
qdev_init_gpio_in(dev, pcf8574_gpio_set, ARRAY_SIZE(s->handler));
qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler));
qdev_init_gpio_out_named(dev, &s->intrq, "nINT", 1);
}
static void pcf8574_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
k->recv = pcf8574_rx;
k->send = pcf8574_tx;
dc->realize = pcf8574_realize;
dc->reset = pcf8574_reset;
dc->vmsd = &vmstate_pcf8574;
}
static const TypeInfo pcf8574_infos[] = {
{
.name = TYPE_PCF8574,
.parent = TYPE_I2C_SLAVE,
.instance_size = sizeof(PCF8574State),
.class_init = pcf8574_class_init,
}
};
DEFINE_TYPES(pcf8574_infos);

0
hw/ide/ahci_internal.h → hw/ide/ahci-internal.h
View File

2
hw/ide/ahci.c
View File

@ -37,7 +37,7 @@
#include "hw/ide/pci.h"
#include "hw/ide/ahci-pci.h"
#include "hw/ide/ahci-sysbus.h"
#include "ahci_internal.h"
#include "ahci-internal.h"
#include "ide-internal.h"
#include "trace.h"

2
hw/ide/ich.c
View File

@ -70,7 +70,7 @@
#include "sysemu/dma.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci-pci.h"
#include "ahci_internal.h"
#include "ahci-internal.h"
#define ICH9_MSI_CAP_OFFSET 0x80
#define ICH9_SATA_CAP_OFFSET 0xA8

1
hw/misc/ivshmem.c
View File

@ -832,6 +832,7 @@ static void ivshmem_write_config(PCIDevice *pdev, uint32_t address,
static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
{
ERRP_GUARD();
IVShmemState *s = IVSHMEM_COMMON(dev);
Error *err = NULL;
uint8_t *pci_conf;

56
hw/pci/pcie.c
View File

@ -28,6 +28,7 @@
#include "hw/pci/pcie_regs.h"
#include "hw/pci/pcie_port.h"
#include "qemu/range.h"
#include "trace.h"
//#define DEBUG_PCIE
#ifdef DEBUG_PCIE
@ -45,6 +46,23 @@ static bool pcie_sltctl_powered_off(uint16_t sltctl)
&& (sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_OFF;
}
static const char *pcie_led_state_to_str(uint16_t value)
{
switch (value) {
case PCI_EXP_SLTCTL_PWR_IND_ON:
case PCI_EXP_SLTCTL_ATTN_IND_ON:
return "on";
case PCI_EXP_SLTCTL_PWR_IND_BLINK:
case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
return "blink";
case PCI_EXP_SLTCTL_PWR_IND_OFF:
case PCI_EXP_SLTCTL_ATTN_IND_OFF:
return "off";
default:
return "invalid";
}
}
/***************************************************************************
* pci express capability helper functions
*/
@ -735,6 +753,28 @@ void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta)
*slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
}
static void find_child_fn(PCIBus *bus, PCIDevice *dev, void *opaque)
{
PCIDevice **child = opaque;
if (!*child) {
*child = dev;
}
}
/*
* Returns the plugged device or first function of multifunction plugged device
*/
static PCIDevice *pcie_cap_slot_find_child(PCIDevice *dev)
{
PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
PCIDevice *child = NULL;
pci_for_each_device(sec_bus, pci_bus_num(sec_bus), find_child_fn, &child);
return child;
}
void pcie_cap_slot_write_config(PCIDevice *dev,
uint16_t old_slt_ctl, uint16_t old_slt_sta,
uint32_t addr, uint32_t val, int len)
@ -779,6 +819,22 @@ void pcie_cap_slot_write_config(PCIDevice *dev,
sltsta);
}
if (trace_event_get_state_backends(TRACE_PCIE_CAP_SLOT_WRITE_CONFIG)) {
DeviceState *parent = DEVICE(dev);
DeviceState *child = DEVICE(pcie_cap_slot_find_child(dev));
trace_pcie_cap_slot_write_config(
parent->canonical_path,
child ? child->canonical_path : "no-child",
(sltsta & PCI_EXP_SLTSTA_PDS) ? "present" : "not present",
pcie_led_state_to_str(old_slt_ctl & PCI_EXP_SLTCTL_PIC),
pcie_led_state_to_str(val & PCI_EXP_SLTCTL_PIC),
pcie_led_state_to_str(old_slt_ctl & PCI_EXP_SLTCTL_AIC),
pcie_led_state_to_str(val & PCI_EXP_SLTCTL_AIC),
(old_slt_ctl & PCI_EXP_SLTCTL_PWR_OFF) ? "off" : "on",
(val & PCI_EXP_SLTCTL_PWR_OFF) ? "off" : "on");
}
/*
* If the slot is populated, power indicator is off and power
* controller is off, it is safe to detach the devices.

46
hw/pci/shpc.c
View File

@ -8,6 +8,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/msi.h"
#include "trace.h"
/* TODO: model power only and disabled slot states. */
/* TODO: handle SERR and wakeups */
@ -123,6 +124,34 @@
#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
static const char *shpc_led_state_to_str(uint8_t value)
{
switch (value) {
case SHPC_LED_ON:
return "on";
case SHPC_LED_BLINK:
return "blink";
case SHPC_LED_OFF:
return "off";
default:
return "invalid";
}
}
static const char *shpc_slot_state_to_str(uint8_t value)
{
switch (value) {
case SHPC_STATE_PWRONLY:
return "power-only";
case SHPC_STATE_ENABLED:
return "enabled";
case SHPC_STATE_DISABLED:
return "disabled";
default:
return "invalid";
}
}
static uint8_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
{
uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
@ -302,6 +331,23 @@ static void shpc_slot_command(PCIDevice *d, uint8_t target,
shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
}
if (trace_event_get_state_backends(TRACE_SHPC_SLOT_COMMAND)) {
DeviceState *parent = DEVICE(d);
int pci_slot = SHPC_IDX_TO_PCI(slot);
DeviceState *child =
DEVICE(shpc->sec_bus->devices[PCI_DEVFN(pci_slot, 0)]);
trace_shpc_slot_command(
parent->canonical_path, pci_slot,
child ? child->canonical_path : "no-child",
shpc_led_state_to_str(old_power),
shpc_led_state_to_str(power),
shpc_led_state_to_str(old_attn),
shpc_led_state_to_str(attn),
shpc_slot_state_to_str(old_state),
shpc_slot_state_to_str(state));
}
if (!shpc_slot_is_off(old_state, old_power, old_attn) &&
shpc_slot_is_off(state, power, attn))
{

6
hw/pci/trace-events
View File

@ -16,3 +16,9 @@ msix_write_config(char *name, bool enabled, bool masked) "dev %s enabled %d mask
sriov_register_vfs(const char *name, int slot, int function, int num_vfs) "%s %02x:%x: creating %d vf devs"
sriov_unregister_vfs(const char *name, int slot, int function, int num_vfs) "%s %02x:%x: Unregistering %d vf devs"
sriov_config_write(const char *name, int slot, int fun, uint32_t offset, uint32_t val, uint32_t len) "%s %02x:%x: sriov offset 0x%x val 0x%x len %d"
# pcie.c
pcie_cap_slot_write_config(const char *parent, const char *child, const char *pds, const char *old_pic, const char *new_pic, const char *old_aic, const char *new_aic, const char *old_power, const char *new_power) "%s > %s: pds: %s, pic: %s->%s, aic: %s->%s, power: %s->%s"
# shpc.c
shpc_slot_command(const char *parent, int pci_slot, const char *child, const char *old_pic, const char *new_pic, const char *old_aic, const char *new_aic, const char *old_state, const char *new_state) "%s[%d] > %s: pic: %s->%s, aic: %s->%s, state: %s->%s"

24
hw/ppc/sam460ex.c
View File

@ -33,6 +33,7 @@
#include "hw/char/serial.h"
#include "hw/i2c/ppc4xx_i2c.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/ide/pci.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/ppc/fdt.h"
#include "hw/qdev-properties.h"
@ -449,15 +450,27 @@ static void sam460ex_init(MachineState *machine)
/* PCI devices */
pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
/* SoC has a single SATA port but we don't emulate that yet
/*
* SoC has a single SATA port but we don't emulate that
* However, firmware and usual clients have driver for SiI311x
* so add one for convenience by default */
* PCI SATA card so add one for convenience by default
*/
if (defaults_enabled()) {
pci_create_simple(pci_bus, -1, "sii3112");
PCIIDEState *s = PCI_IDE(pci_create_simple(pci_bus, -1, "sii3112"));
DriveInfo *di;
di = drive_get_by_index(IF_IDE, 0);
if (di) {
ide_bus_create_drive(&s->bus[0], 0, di);
}
/* Use index 2 only if 1 does not exist, this allows -cdrom */
di = drive_get_by_index(IF_IDE, 1) ?: drive_get_by_index(IF_IDE, 2);
if (di) {
ide_bus_create_drive(&s->bus[1], 0, di);
}
}
/* SoC has 4 UARTs
* but board has only one wired and two are present in fdt */
/* SoC has 4 UARTs but board has only one wired and two described in fdt */
if (serial_hd(0) != NULL) {
serial_mm_init(get_system_memory(), 0x4ef600300, 0,
qdev_get_gpio_in(uic[1], 1),
@ -531,6 +544,7 @@ static void sam460ex_machine_init(MachineClass *mc)
{
mc->desc = "aCube Sam460ex";
mc->init = sam460ex_init;
mc->block_default_type = IF_IDE;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
mc->default_ram_size = 512 * MiB;
mc->default_ram_id = "ppc4xx.sdram";

9
hw/sparc64/sun4u.c
View File

@ -360,8 +360,13 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
pci_dev->config[0x09] = 0x00; // programming i/f
pci_dev->config[0x0D] = 0x0a; // latency_timer
memory_region_init_alias(&s->bar0, OBJECT(s), "bar0",
pci_address_space_io(pci_dev), 0, 0x1000000);
/*
* BAR0 is accessed by OpenBSD but not for ebus device access: allow any
* memory access to this region to succeed which allows the OpenBSD kernel
* to boot.
*/
memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s,
"bar0", 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1",
pci_address_space_io(pci_dev), 0, 0x8000);

15
include/hw/gpio/pcf8574.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* NXP PCF8574 8-port I2C GPIO expansion chip.
*
* Copyright (c) 2024 KNS Group (YADRO).
* Written by Dmitrii Sharikhin <d.sharikhin@yadro.com>
*/
#ifndef _HW_GPIO_PCF8574
#define _HW_GPIO_PCF8574
#define TYPE_PCF8574 "pcf8574"
#endif /* _HW_GPIO_PCF8574 */

2
meson.build
View File

@ -66,7 +66,7 @@ if host_os == 'windows' and add_languages('cpp', required: false, native: false)
cxx = meson.get_compiler('cpp')
endif
if host_os == 'darwin' and \
add_languages('objc', required: get_option('cocoa'), native: false)
add_languages('objc', required: true, native: false)
all_languages += ['objc']
objc = meson.get_compiler('objc')
endif