Patch queue for s390 - 2017-04-25
Two simple fixes this time around: - fix BQL for s390 virtio target - Fix SIGP emulation -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJY/zW2AAoJECszeR4D/txgnsUP/AjchRi1iPFmiIJpEZxo6L4e RZfylCvHWwqplmu2BgTurA+X+qEiHSu6awRubFXCAU4pyBpXt2ejoJEzkTKI1MK/ HYsxeCz8+uasdjjP0XS8K3KQaEdIH5VXxnYzDHHL40AtxGYdFEy7PyHi47abZYBG 9I0O4G3E9KRmZD2mVdlomsRv70WCI4/z3xBsoGQH8GOcxuySwvPlvzIevSeI1HzT SPdkz0eU9vZSfVhKy7YU4Kj6w3EPVmeXPCEGbEhOy0pzJYPgG9ST//WyOegjMr6Y UYsvhKiG90WebiXgxN2WaiBMReEpBI2/fUsFlLskpX/LulhJDEmMIOYb9sD5in7I q6fU/KItU00zwwBXz/8ID8MlZQb1xmSuy327+LwYOX2AjN+4G/CNx4iQEjLLNF+p ecLeq7tKycs7yNK5LlE8XfBZnDTCniuQCFbq/d+wT6slCPopmm96Omt++8iY/vyk 3mFEhEat/0Tm3oPrkbh2IlcYCyvfZWy963pQ/DnsSfVcjl88GQyzQGFuCVN8HZIo 8icmqPid2jyhMZtdjPtDHhpAuhWwo1o+vzR0bZxwjDj4/UJ00/dBHSUmu2gFIUUb 0/xQacvY63qb+FuQynw2eTFfxZoOPAmOIb/HAY+N/GreQNXIkbtrjVM7IQmfaB5b aZPwxmqZ7cwU8YTfH25O =Jzre -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/agraf/tags/signed-s390-for-upstream' into staging Patch queue for s390 - 2017-04-25 Two simple fixes this time around: - fix BQL for s390 virtio target - Fix SIGP emulation # gpg: Signature made Tue 25 Apr 2017 12:40:38 BST # gpg: using RSA key 0x2B33791E03FEDC60 # gpg: Good signature from "Alexander Graf <agraf@suse.de>" # gpg: aka "Alexander Graf <alex@csgraf.de>" # Primary key fingerprint: 7F2A 4C87 F94C 5EFE DBC3 75DC 1631 30DA 5B24 530A # Subkey fingerprint: 54D3 364F A6C3 60FF AF81 EB53 2B33 791E 03FE DC60 * remotes/agraf/tags/signed-s390-for-upstream: s390x/misc_helper.c: wrap s390_virtio_hypercall in BQL target-s390x: Mask the SIGP order_code to 8bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
fe491fa85c
@ -288,7 +288,9 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint32_t num)
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switch (num) {
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case 0x500:
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/* KVM hypercall */
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qemu_mutex_lock_iothread();
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r = s390_virtio_hypercall(env);
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qemu_mutex_unlock_iothread();
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break;
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case 0x44:
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/* yield */
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@ -515,7 +517,8 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
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/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
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as parameter (input). Status (output) is always R1. */
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switch (order_code) {
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/* sigp contains the order code in bit positions 56-63, mask it here. */
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switch (order_code & 0xff) {
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case SIGP_SET_ARCH:
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/* switch arch */
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break;
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