target-i386: Add NPT support
This implements NPT suport for SVM by hooking into x86_cpu_handle_mmu_fault where it reads the stage-1 page table. Whether we need to perform this 2nd stage translation, and how, is decided during vmrun and stored in hflags2, along with nested_cr3 and nested_pg_mode. As get_hphys performs a direct cpu_vmexit in case of NPT faults, we need retaddr in that function. To avoid changing the signature of cpu_handle_mmu_fault, this passes the value from tlb_fill to get_hphys via the CPU state. This was tested successfully via the Jailhouse hypervisor. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <567473a0-6005-5843-4c73-951f476085ca@web.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
76b004d10d
commit
fe441054bb
@ -749,7 +749,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
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CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
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#define TCG_EXT4_FEATURES 0
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#define TCG_SVM_FEATURES 0
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#define TCG_SVM_FEATURES CPUID_SVM_NPT
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#define TCG_KVM_FEATURES 0
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#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
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CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
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@ -211,6 +211,7 @@ typedef enum X86Seg {
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#define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
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#define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
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#define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
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#define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
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#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
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#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
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@ -218,6 +219,7 @@ typedef enum X86Seg {
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#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
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#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
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#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
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#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
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#define CR0_PE_SHIFT 0
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#define CR0_MP_SHIFT 1
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@ -1265,12 +1267,16 @@ typedef struct CPUX86State {
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uint16_t intercept_dr_read;
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uint16_t intercept_dr_write;
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uint32_t intercept_exceptions;
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uint64_t nested_cr3;
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uint32_t nested_pg_mode;
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uint8_t v_tpr;
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/* KVM states, automatically cleared on reset */
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uint8_t nmi_injected;
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uint8_t nmi_pending;
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uintptr_t retaddr;
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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@ -157,6 +157,209 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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#else
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static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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{
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CPUX86State *env = &X86_CPU(cs)->env;
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uint64_t rsvd_mask = PG_HI_RSVD_MASK;
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uint64_t ptep, pte;
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uint64_t exit_info_1 = 0;
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target_ulong pde_addr, pte_addr;
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uint32_t page_offset;
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int page_size;
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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return gphys;
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}
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if (!(env->nested_pg_mode & SVM_NPT_NXE)) {
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rsvd_mask |= PG_NX_MASK;
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}
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if (env->nested_pg_mode & SVM_NPT_PAE) {
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uint64_t pde, pdpe;
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target_ulong pdpe_addr;
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#ifdef TARGET_X86_64
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if (env->nested_pg_mode & SVM_NPT_LMA) {
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uint64_t pml5e;
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uint64_t pml4e_addr, pml4e;
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pml5e = env->nested_cr3;
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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pml4e_addr = (pml5e & PG_ADDRESS_MASK) +
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(((gphys >> 39) & 0x1ff) << 3);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml4e & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml4e & PG_ACCESSED_MASK)) {
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pml4e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml4e_addr, pml4e);
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}
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ptep &= pml4e ^ PG_NX_MASK;
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pdpe_addr = (pml4e & PG_ADDRESS_MASK) +
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(((gphys >> 30) & 0x1ff) << 3);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pdpe & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pdpe ^ PG_NX_MASK;
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if (!(pdpe & PG_ACCESSED_MASK)) {
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pdpe |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pdpe_addr, pdpe);
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}
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if (pdpe & PG_PSE_MASK) {
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/* 1 GB page */
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page_size = 1024 * 1024 * 1024;
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pte_addr = pdpe_addr;
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pte = pdpe;
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goto do_check_protect;
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}
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} else
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#endif
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{
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pdpe_addr = (env->nested_cr3 & ~0x1f) + ((gphys >> 27) & 0x18);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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rsvd_mask |= PG_HI_USER_MASK;
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if (pdpe & (rsvd_mask | PG_NX_MASK)) {
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goto do_fault_rsvd;
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}
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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pde_addr = (pdpe & PG_ADDRESS_MASK) + (((gphys >> 21) & 0x1ff) << 3);
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pde = x86_ldq_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pde & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pde ^ PG_NX_MASK;
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if (pde & PG_PSE_MASK) {
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/* 2 MB page */
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page_size = 2048 * 1024;
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pte_addr = pde_addr;
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pte = pde;
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goto do_check_protect;
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}
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/* 4 KB page */
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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}
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pte_addr = (pde & PG_ADDRESS_MASK) + (((gphys >> 12) & 0x1ff) << 3);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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/* combine pde and pte nx, user and rw protections */
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ptep &= pte ^ PG_NX_MASK;
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page_size = 4096;
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} else {
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uint32_t pde;
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/* page directory entry */
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pde_addr = (env->nested_cr3 & ~0xfff) + ((gphys >> 20) & 0xffc);
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pde = x86_ldl_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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ptep = pde | PG_NX_MASK;
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/* if PSE bit is set, then we use a 4MB page */
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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page_size = 4096 * 1024;
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pte_addr = pde_addr;
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/* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
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* Leave bits 20-13 in place for setting accessed/dirty bits below.
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*/
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pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
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rsvd_mask = 0x200000;
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goto do_check_protect_pse36;
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}
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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}
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/* page directory entry */
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pte_addr = (pde & ~0xfff) + ((gphys >> 10) & 0xffc);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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/* combine pde and pte user and rw protections */
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ptep &= pte | PG_NX_MASK;
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page_size = 4096;
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rsvd_mask = 0;
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}
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do_check_protect:
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rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
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do_check_protect_pse36:
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep ^= PG_NX_MASK;
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if (!(ptep & PG_USER_MASK)) {
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goto do_fault_protect;
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}
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if (ptep & PG_NX_MASK) {
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if (access_type == MMU_INST_FETCH) {
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goto do_fault_protect;
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}
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*prot &= ~PAGE_EXEC;
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}
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if (!(ptep & PG_RW_MASK)) {
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if (access_type == MMU_DATA_STORE) {
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goto do_fault_protect;
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}
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*prot &= ~PAGE_WRITE;
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}
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pte &= PG_ADDRESS_MASK & ~(page_size - 1);
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page_offset = gphys & (page_size - 1);
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return pte + page_offset;
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do_fault_rsvd:
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exit_info_1 |= SVM_NPTEXIT_RSVD;
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do_fault_protect:
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exit_info_1 |= SVM_NPTEXIT_P;
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do_fault:
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x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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gphys);
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exit_info_1 |= SVM_NPTEXIT_US;
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if (access_type == MMU_DATA_STORE) {
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exit_info_1 |= SVM_NPTEXIT_RW;
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} else if (access_type == MMU_INST_FETCH) {
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exit_info_1 |= SVM_NPTEXIT_ID;
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}
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if (prot) {
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exit_info_1 |= SVM_NPTEXIT_GPA;
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} else { /* page table access */
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exit_info_1 |= SVM_NPTEXIT_GPT;
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}
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
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}
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/* return value:
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* -1 = cannot handle fault
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* 0 = nothing more to do
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@ -224,6 +427,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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if (la57) {
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pml5e_addr = ((env->cr[3] & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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pml5e_addr = get_hphys(cs, pml5e_addr, MMU_DATA_STORE, NULL);
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pml5e = x86_ldq_phys(cs, pml5e_addr);
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if (!(pml5e & PG_PRESENT_MASK)) {
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goto do_fault;
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@ -243,6 +447,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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pml4e_addr = get_hphys(cs, pml4e_addr, MMU_DATA_STORE, false);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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goto do_fault;
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@ -257,6 +462,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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ptep &= pml4e ^ PG_NX_MASK;
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pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
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a20_mask;
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pdpe_addr = get_hphys(cs, pdpe_addr, MMU_DATA_STORE, NULL);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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@ -282,6 +488,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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/* XXX: load them when cr3 is loaded ? */
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pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
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a20_mask;
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pdpe_addr = get_hphys(cs, pdpe_addr, MMU_DATA_STORE, false);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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@ -295,6 +502,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
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a20_mask;
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pde_addr = get_hphys(cs, pde_addr, MMU_DATA_STORE, NULL);
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pde = x86_ldq_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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@ -317,6 +525,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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}
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pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
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a20_mask;
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pte_addr = get_hphys(cs, pte_addr, MMU_DATA_STORE, NULL);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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@ -333,6 +542,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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/* page directory entry */
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pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
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a20_mask;
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pde_addr = get_hphys(cs, pde_addr, MMU_DATA_STORE, NULL);
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pde = x86_ldl_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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@ -360,6 +570,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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/* page directory entry */
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pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
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a20_mask;
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pte_addr = get_hphys(cs, pte_addr, MMU_DATA_STORE, NULL);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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@ -442,12 +653,13 @@ do_check_protect_pse36:
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/* align to page_size */
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pte &= PG_ADDRESS_MASK & ~(page_size - 1);
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page_offset = addr & (page_size - 1);
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paddr = get_hphys(cs, pte + page_offset, is_write1, &prot);
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/* Even if 4MB pages, we map only one 4KB page in the cache to
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avoid filling it too fast */
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vaddr = addr & TARGET_PAGE_MASK;
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page_offset = vaddr & (page_size - 1);
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paddr = pte + page_offset;
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paddr &= TARGET_PAGE_MASK;
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assert(prot & (1 << is_write1));
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tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env),
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@ -935,6 +935,26 @@ static const VMStateDescription vmstate_msr_virt_ssbd = {
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}
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};
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static bool svm_npt_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return !!(env->hflags2 & HF2_NPT_MASK);
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}
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static const VMStateDescription vmstate_svm_npt = {
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.name = "cpu/svn_npt",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = svm_npt_needed,
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.fields = (VMStateField[]){
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VMSTATE_UINT64(env.nested_cr3, X86CPU),
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VMSTATE_UINT32(env.nested_pg_mode, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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VMStateDescription vmstate_x86_cpu = {
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.name = "cpu",
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.version_id = 12,
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@ -1059,6 +1079,7 @@ VMStateDescription vmstate_x86_cpu = {
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&vmstate_mcg_ext_ctl,
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&vmstate_msr_intel_pt,
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&vmstate_msr_virt_ssbd,
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&vmstate_svm_npt,
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NULL
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}
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};
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@ -202,13 +202,13 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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int ret;
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env->retaddr = retaddr;
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ret = x86_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
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if (ret) {
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr);
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}
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}
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@ -130,6 +130,20 @@
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#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
|
||||
|
||||
#define SVM_NPT_ENABLED (1 << 0)
|
||||
|
||||
#define SVM_NPT_PAE (1 << 0)
|
||||
#define SVM_NPT_LMA (1 << 1)
|
||||
#define SVM_NPT_NXE (1 << 2)
|
||||
|
||||
#define SVM_NPTEXIT_P (1ULL << 0)
|
||||
#define SVM_NPTEXIT_RW (1ULL << 1)
|
||||
#define SVM_NPTEXIT_US (1ULL << 2)
|
||||
#define SVM_NPTEXIT_RSVD (1ULL << 3)
|
||||
#define SVM_NPTEXIT_ID (1ULL << 4)
|
||||
#define SVM_NPTEXIT_GPA (1ULL << 32)
|
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#define SVM_NPTEXIT_GPT (1ULL << 33)
|
||||
|
||||
struct QEMU_PACKED vmcb_control_area {
|
||||
uint16_t intercept_cr_read;
|
||||
uint16_t intercept_cr_write;
|
||||
|
@ -124,6 +124,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
|
||||
{
|
||||
CPUState *cs = CPU(x86_env_get_cpu(env));
|
||||
target_ulong addr;
|
||||
uint64_t nested_ctl;
|
||||
uint32_t event_inj;
|
||||
uint32_t int_ctl;
|
||||
|
||||
@ -206,6 +207,26 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
|
||||
control.intercept_exceptions
|
||||
));
|
||||
|
||||
nested_ctl = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
|
||||
control.nested_ctl));
|
||||
if (nested_ctl & SVM_NPT_ENABLED) {
|
||||
env->nested_cr3 = x86_ldq_phys(cs,
|
||||
env->vm_vmcb + offsetof(struct vmcb,
|
||||
control.nested_cr3));
|
||||
env->hflags2 |= HF2_NPT_MASK;
|
||||
|
||||
env->nested_pg_mode = 0;
|
||||
if (env->cr[4] & CR4_PAE_MASK) {
|
||||
env->nested_pg_mode |= SVM_NPT_PAE;
|
||||
}
|
||||
if (env->hflags & HF_LMA_MASK) {
|
||||
env->nested_pg_mode |= SVM_NPT_LMA;
|
||||
}
|
||||
if (env->efer & MSR_EFER_NXE) {
|
||||
env->nested_pg_mode |= SVM_NPT_NXE;
|
||||
}
|
||||
}
|
||||
|
||||
/* enable intercepts */
|
||||
env->hflags |= HF_SVMI_MASK;
|
||||
|
||||
@ -616,6 +637,7 @@ void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
|
||||
x86_stl_phys(cs,
|
||||
env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0);
|
||||
}
|
||||
env->hflags2 &= ~HF2_NPT_MASK;
|
||||
|
||||
/* Save the VM state in the vmcb */
|
||||
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.es),
|
||||
|
Loading…
Reference in New Issue
Block a user