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Fix PowerPC initialisation and first reset:

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reset must occur after we defined the CPU features.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3317 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-10-03 01:06:57 +00:00
parent 00af685fc9
commit fe33cc7103
3 changed files with 20 additions and 12 deletions
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6
hw/ppc_chrp.c
View File

@ -327,9 +327,6 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
/* init CPUs */
env = cpu_init();
qemu_register_reset(&cpu_ppc_reset, env);
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
if (cpu_model == NULL)
cpu_model = "default";
ppc_find_by_name(cpu_model, &def);
@ -338,9 +335,12 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
}
for (i = 0; i < smp_cpus; i++) {
cpu_ppc_register(env, def);
cpu_ppc_reset(env);
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
env->osi_call = vga_osi_call;
qemu_register_reset(&cpu_ppc_reset, env);
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
envs[i] = env;
}

21
hw/ppc_prep.c
View File

@ -26,6 +26,9 @@
//#define HARD_DEBUG_PPC_IO
//#define DEBUG_PPC_IO
/* SMP is not enabled, for now */
#define MAX_CPUS 1
#define BIOS_FILENAME "ppc_rom.bin"
#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000
@ -521,7 +524,7 @@ static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env;
CPUState *env, *envs[MAX_CPUS];
char buf[1024];
m48t59_t *nvram;
int PPC_io_memory;
@ -539,20 +542,22 @@ static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
linux_boot = (kernel_filename != NULL);
/* init CPUs */
env = cpu_init();
qemu_register_reset(&cpu_ppc_reset, env);
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
if (cpu_model == NULL)
cpu_model = "default";
ppc_find_by_name(cpu_model, &def);
if (def == NULL) {
cpu_abort(env, "Unable to find PowerPC CPU definition\n");
}
cpu_ppc_register(env, def);
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
for (i = 0; i < smp_cpus; i++) {
cpu_ppc_register(env, def);
cpu_ppc_reset(env);
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
qemu_register_reset(&cpu_ppc_reset, env);
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
envs[i] = env;
}
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

5
target-ppc/helper.c
View File

@ -2788,8 +2788,12 @@ void cpu_ppc_reset (void *opaque)
#if defined(CONFIG_USER_ONLY)
msr_fp = 1; /* Allow floating point exceptions */
msr_pr = 1;
#else
#if defined(TARGET_PPC64)
env->nip = 0x00000100;
#else
env->nip = 0xFFFFFFFC;
#endif
ppc_tlb_invalidate_all(env);
#endif
do_compute_hflags(env);
@ -2810,7 +2814,6 @@ CPUPPCState *cpu_ppc_init (void)
if (!env)
return NULL;
cpu_exec_init(env);
cpu_ppc_reset(env);
return env;
}