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target/arm: Fix svep width in arm_gen_dynamic_svereg_xml

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Define svep based on the size of the predicates,
not the primary vector registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-27 11:33:22 -10:00 committed by Peter Maydell
parent 5cd5fa756e
commit fdfb214cf0
1 changed files with 1 additions and 1 deletions
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2
target/arm/gdbstub64.c
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@ -297,7 +297,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
/* Create the predicate vector type. */
g_string_append_printf(s,
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
reg_width / 8);
pred_width / 8);
/* Define the vector registers. */
for (i = 0; i < 32; i++) {