Use "hash" more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't (quite) get the hash value for the ppc hashed page table. Instead it gets the hash shifted - effectively the offset of the hash bucket within the hash page table. As well, as being different to the normal use of plain "hash" in the architecture documentation, this usage necessitates some awkward 32/64 dependent masks and shifts which clutter up the path in get_segment(). This patch alters the code to use raw hash values through get_segment() including storing raw hashes instead of pte group offsets in the ctx structure. This cleans up the path noticeably. This does necessitate 32/64 dependent shifts when the hash values are taken out of the ctx structure and used, but those paths already have 32/64 bit variants so this is less awkward than it was in get_segment(). Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson
Alexander Graf
parent
bb593904c1
commit
fda6a0ecc6
@ -367,6 +367,9 @@ union ppc_tlb_t {
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#define SDR_64_HTABSIZE 0x000000000000001FULL
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#endif /* defined(TARGET_PPC64 */
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#define HASH_PTE_SIZE_32 8
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#define HASH_PTE_SIZE_64 16
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typedef struct ppc_slb_t ppc_slb_t;
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struct ppc_slb_t {
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uint64_t esid;
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@ -744,7 +747,7 @@ struct mmu_ctx_t {
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target_phys_addr_t raddr; /* Real address */
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target_phys_addr_t eaddr; /* Effective address */
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int prot; /* Protection bits */
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target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
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target_phys_addr_t hash[2]; /* Pagetable hash values */
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target_ulong ptem; /* Virtual segment ID | API */
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int key; /* Access key */
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int nx; /* Non-execute area */
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@ -567,21 +567,30 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
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return ret;
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}
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/* PTE table lookup */
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static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
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int type, int target_page_bits)
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static inline target_phys_addr_t get_pteg_offset(CPUState *env,
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target_phys_addr_t hash,
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int pte_size)
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{
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target_ulong base, pte0, pte1;
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return (hash * pte_size * 8) & env->htab_mask;
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}
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/* PTE table lookup */
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static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h,
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int rw, int type, int target_page_bits)
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{
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target_phys_addr_t pteg_off;
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target_ulong pte0, pte1;
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int i, good = -1;
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int ret, r;
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ret = -1; /* No entry found */
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base = ctx->pg_addr[h];
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pteg_off = get_pteg_offset(env, ctx->hash[h],
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is_64b ? HASH_PTE_SIZE_64 : HASH_PTE_SIZE_32);
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for (i = 0; i < 8; i++) {
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#if defined(TARGET_PPC64)
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if (is_64b) {
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pte0 = ldq_phys(base + (i * 16));
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pte1 = ldq_phys(base + (i * 16) + 8);
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pte0 = ldq_phys(env->htab_base + pteg_off + (i * 16));
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pte1 = ldq_phys(env->htab_base + pteg_off + (i * 16) + 8);
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/* We have a TLB that saves 4K pages, so let's
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* split a huge page to 4k chunks */
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@ -592,17 +601,17 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
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r = pte64_check(ctx, pte0, pte1, h, rw, type);
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LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
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TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
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base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
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pteg_base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
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(int)((pte0 >> 1) & 1), ctx->ptem);
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} else
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#endif
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{
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pte0 = ldl_phys(base + (i * 8));
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pte1 = ldl_phys(base + (i * 8) + 4);
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pte0 = ldl_phys(env->htab_base + pteg_off + (i * 8));
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pte1 = ldl_phys(env->htab_base + pteg_off + (i * 8) + 4);
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r = pte32_check(ctx, pte0, pte1, h, rw, type);
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LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
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TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
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base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
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pteg_base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
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(int)((pte0 >> 6) & 1), ctx->ptem);
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}
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switch (r) {
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@ -638,11 +647,13 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
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if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
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#if defined(TARGET_PPC64)
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if (is_64b) {
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stq_phys_notdirty(base + (good * 16) + 8, pte1);
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stq_phys_notdirty(env->htab_base + pteg_off + (good * 16) + 8,
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pte1);
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} else
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#endif
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{
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stl_phys_notdirty(base + (good * 8) + 4, pte1);
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stl_phys_notdirty(env->htab_base + pteg_off + (good * 8) + 4,
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pte1);
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}
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}
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}
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@ -650,17 +661,17 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
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return ret;
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}
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static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
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int target_page_bits)
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static inline int find_pte32(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
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int type, int target_page_bits)
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{
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return _find_pte(ctx, 0, h, rw, type, target_page_bits);
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return _find_pte(env, ctx, 0, h, rw, type, target_page_bits);
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}
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#if defined(TARGET_PPC64)
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static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
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int target_page_bits)
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static inline int find_pte64(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
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int type, int target_page_bits)
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{
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return _find_pte(ctx, 1, h, rw, type, target_page_bits);
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return _find_pte(env, ctx, 1, h, rw, type, target_page_bits);
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}
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#endif
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@ -669,10 +680,10 @@ static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
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{
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64)
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return find_pte64(ctx, h, rw, type, target_page_bits);
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return find_pte64(env, ctx, h, rw, type, target_page_bits);
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#endif
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return find_pte32(ctx, h, rw, type, target_page_bits);
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return find_pte32(env, ctx, h, rw, type, target_page_bits);
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}
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#if defined(TARGET_PPC64)
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@ -788,19 +799,12 @@ int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt)
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#endif /* defined(TARGET_PPC64) */
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/* Perform segment based translation */
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static inline target_phys_addr_t get_pgaddr(target_phys_addr_t htab_base,
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target_phys_addr_t htab_mask,
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target_phys_addr_t hash)
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{
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return htab_base | (hash & htab_mask);
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}
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static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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{
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target_phys_addr_t hash;
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target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
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int ds, vsid_sh, pr, target_page_bits;
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target_ulong sr, vsid, pgidx, page_mask;
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int ds, pr, target_page_bits;
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int ret, ret2;
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pr = msr_pr;
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@ -823,8 +827,6 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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ds = 0;
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ctx->nx = !!(slb->vsid & SLB_VSID_N);
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ctx->eaddr = eaddr;
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vsid_mask = 0x00003FFFFFFFFF80ULL;
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vsid_sh = 7;
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} else
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#endif /* defined(TARGET_PPC64) */
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{
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@ -835,8 +837,6 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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ds = sr & 0x80000000 ? 1 : 0;
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ctx->nx = sr & 0x10000000 ? 1 : 0;
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vsid = sr & 0x00FFFFFF;
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vsid_mask = 0x01FFFFC0;
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vsid_sh = 6;
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target_page_bits = TARGET_PAGE_BITS;
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
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@ -851,27 +851,22 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || ctx->nx == 0) {
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/* Page address translation */
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/* Primary table address */
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pgidx = (eaddr & page_mask) >> target_page_bits;
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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/* XXX: this is false for 1 TB segments */
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hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
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hash = vsid ^ pgidx;
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} else
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#endif
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{
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hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
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hash = vsid ^ pgidx;
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}
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->pg_addr[0] = get_pgaddr(env->htab_base, env->htab_mask, hash);
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/* Secondary table address */
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hash = (~hash) & vsid_mask;
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->pg_addr[1] = get_pgaddr(env->htab_base, env->htab_mask, hash);
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ctx->hash[0] = hash;
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ctx->hash[1] = ~hash;
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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/* Only 5 bits of the page index are used in the AVPN */
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@ -895,9 +890,9 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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} else {
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx " pg_addr=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, pgidx, hash,
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ctx->pg_addr[0]);
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, pgidx,
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ctx->hash[0]);
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/* Primary table lookup */
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ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
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if (ret < 0) {
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@ -908,7 +903,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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" hash=" TARGET_FMT_plx " pg_addr="
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TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, pgidx, hash,
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ctx->pg_addr[1]);
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ctx->hash[1]);
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ret2 = find_pte(env, ctx, 1, rw, type,
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target_page_bits);
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if (ret2 != -1)
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@ -1460,8 +1455,10 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
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tlb_miss:
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env->error_code |= ctx.key << 19;
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env->spr[SPR_HASH1] = ctx.pg_addr[0];
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env->spr[SPR_HASH2] = ctx.pg_addr[1];
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env->spr[SPR_HASH1] = env->htab_base +
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get_pteg_offset(env, ctx.hash[0], HASH_PTE_SIZE_32);
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env->spr[SPR_HASH2] = env->htab_base +
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get_pteg_offset(env, ctx.hash[1], HASH_PTE_SIZE_32);
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break;
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case POWERPC_MMU_SOFT_74xx:
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if (rw == 1) {
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