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hw/arm/pxa2xx: Replace printf() call by qemu_log_mask() 

Replace printf() calls by qemu_log_mask(), which is disabled
by default. This avoid flooding the terminal when fuzzing the
device.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200525114123.21317-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-06-02 13:44:35 +01:00 committed by Peter Maydell
parent 3a37f23979
commit fc417e5b57
1 changed files with 49 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
hw/arm/pxa2xx.c
View File

@ -26,6 +26,7 @@
#include "sysemu/blockdev.h"
#include "sysemu/qtest.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
static struct {
hwaddr io_base;
@ -112,7 +113,9 @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
return s->pm_regs[addr >> 2];
default:
fail:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
@ -143,8 +146,9 @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr,
s->pm_regs[addr >> 2] = value;
break;
}
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
}
@ -185,7 +189,9 @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
return s->cm_regs[CCCR >> 2] | (3 << 28);
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
@ -210,7 +216,9 @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr,
break;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
}
@ -415,7 +423,9 @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
return s->mm_regs[addr >> 2];
/* fall through */
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
@ -434,7 +444,9 @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr,
}
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
}
@ -641,7 +653,9 @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
case SSACD:
return s->ssacd;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
@ -733,7 +747,9 @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
break;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
}
@ -995,7 +1011,9 @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
else
return s->last_swcr;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
@ -1101,7 +1119,9 @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
break;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
}
}
@ -1354,7 +1374,9 @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
s->ibmr = 0;
return s->ibmr;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
@ -1427,7 +1449,9 @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
break;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
}
}
@ -1628,7 +1652,9 @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
}
return 0;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
@ -1685,7 +1711,9 @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
}
break;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
}
}
@ -1870,7 +1898,9 @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
case ICFOR:
return s->rx_len;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
@ -1922,7 +1952,9 @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
case ICFOR:
break;
default:
printf("%s: Bad register " REG_FMT "\n", __func__, addr);
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
}
}