hw/arm: Add MFT device to NPCM7xx Soc
This patch adds the recently implemented MFT device to the NPCM7XX SoC file. Reviewed-by: Doug Evans <dje@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210311180855.149764-4-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -45,6 +45,7 @@ Supported devices
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* Pulse Width Modulation (PWM)
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* SMBus controller (SMBF)
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* Ethernet controller (EMC)
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* Tachometer
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Missing devices
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---------------
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@ -63,7 +64,6 @@ Missing devices
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* Peripheral SPI controller (PSPI)
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* SD/MMC host
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* PECI interface
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* Tachometer
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* PCI and PCIe root complex and bridges
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* VDM and MCTP support
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* Serial I/O expansion
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@ -122,6 +122,14 @@ enum NPCM7xxInterrupt {
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NPCM7XX_SMBUS15_IRQ,
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NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
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NPCM7XX_PWM1_IRQ, /* PWM module 1 */
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NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */
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NPCM7XX_MFT1_IRQ, /* MFT module 1 */
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NPCM7XX_MFT2_IRQ, /* MFT module 2 */
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NPCM7XX_MFT3_IRQ, /* MFT module 3 */
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NPCM7XX_MFT4_IRQ, /* MFT module 4 */
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NPCM7XX_MFT5_IRQ, /* MFT module 5 */
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NPCM7XX_MFT6_IRQ, /* MFT module 6 */
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NPCM7XX_MFT7_IRQ, /* MFT module 7 */
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NPCM7XX_EMC2RX_IRQ = 114,
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NPCM7XX_EMC2TX_IRQ,
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NPCM7XX_GPIO0_IRQ = 116,
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@ -172,6 +180,18 @@ static const hwaddr npcm7xx_pwm_addr[] = {
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0xf0104000,
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};
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/* Register base address for each MFT Module */
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static const hwaddr npcm7xx_mft_addr[] = {
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0xf0180000,
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0xf0181000,
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0xf0182000,
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0xf0183000,
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0xf0184000,
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0xf0185000,
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0xf0186000,
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0xf0187000,
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};
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/* Direct memory-mapped access to each SMBus Module. */
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static const hwaddr npcm7xx_smbus_addr[] = {
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0xf0080000,
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@ -417,6 +437,10 @@ static void npcm7xx_init(Object *obj)
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object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
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}
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for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
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object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT);
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}
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for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
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object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
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}
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@ -603,6 +627,19 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
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sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
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}
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/* MFT Modules. Cannot fail. */
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QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_mft_addr) != ARRAY_SIZE(s->mft));
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for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
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SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]);
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qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in",
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qdev_get_clock_out(DEVICE(&s->clk),
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"apb4-clock"));
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sysbus_realize(sbd, &error_abort);
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sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]);
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sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i));
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}
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/*
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* EMC Modules. Cannot fail.
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* The mapping of the device to its netdev backend works as follows:
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@ -680,14 +717,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
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create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
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create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
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create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
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create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
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create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
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create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
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create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB);
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create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB);
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create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB);
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create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB);
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create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB);
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create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
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create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
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create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
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@ -24,6 +24,7 @@
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#include "hw/mem/npcm7xx_mc.h"
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#include "hw/misc/npcm7xx_clk.h"
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#include "hw/misc/npcm7xx_gcr.h"
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#include "hw/misc/npcm7xx_mft.h"
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#include "hw/misc/npcm7xx_pwm.h"
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#include "hw/misc/npcm7xx_rng.h"
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#include "hw/net/npcm7xx_emc.h"
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@ -82,6 +83,7 @@ typedef struct NPCM7xxState {
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NPCM7xxTimerCtrlState tim[3];
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NPCM7xxADCState adc;
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NPCM7xxPWMState pwm[2];
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NPCM7xxMFTState mft[8];
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NPCM7xxOTPState key_storage;
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NPCM7xxOTPState fuse_array;
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NPCM7xxMCState mc;
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