mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix CR ops with complement, thanks to Julian Seward for testing

Browse Source 
and reporting the bug :
* remove bugged CR ops specific micro-ops
* use standard and / or / shift operations instead
* comment not-used-anymore op_store_T1_crf_crf micro-op template.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3501 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-10-31 22:02:17 +00:00
parent a79ee211ce
commit fc0d441e14
3 changed files with 27 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
target-ppc/op.c
View File

@ -651,25 +651,6 @@ void OPPROTO op_store_fpscr (void)
RETURN(); RETURN();
} }
/* crf operations */
void OPPROTO op_getbit_T0 (void)
{
T0 = (T0 >> PARAM1) & 1;
RETURN();
}
void OPPROTO op_getbit_T1 (void)
{
T1 = (T1 >> PARAM1) & 1;
RETURN();
}
void OPPROTO op_setcrfbit (void)
{
T1 = (T1 & (uint32_t)PARAM1) | (T0 << PARAM2);
RETURN();
}
/* Branch */ /* Branch */
#define EIP env->nip #define EIP env->nip
@ -1737,6 +1718,12 @@ void OPPROTO op_sli_T0 (void)
RETURN(); RETURN();
} }
void OPPROTO op_sli_T1 (void)
{
T1 = T1 << PARAM1;
RETURN();
}
void OPPROTO op_srl_T0_T1 (void) void OPPROTO op_srl_T0_T1 (void)
{ {
T0 = (uint32_t)T0 >> T1; T0 = (uint32_t)T0 >> T1;

2
target-ppc/op_template.h
View File

@ -159,11 +159,13 @@ void OPPROTO glue(op_store_T0_crf_crf, REG) (void)
RETURN(); RETURN();
} }
#if 0 // Unused
void OPPROTO glue(op_store_T1_crf_crf, REG) (void) void OPPROTO glue(op_store_T1_crf_crf, REG) (void)
{ {
env->crf[REG] = T1; env->crf[REG] = T1;
RETURN(); RETURN();
} }
#endif
#endif /* REG <= 7 */ #endif /* REG <= 7 */

24
target-ppc/translate.c
View File

@ -120,7 +120,9 @@ static always_inline void func (int n) \
GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf); GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf); GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
#if 0 // Unused
GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
#endif
/* General purpose registers moves */ /* General purpose registers moves */
GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr); GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
@ -3318,15 +3320,27 @@ GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
#define GEN_CRLOGIC(op, opc) \ #define GEN_CRLOGIC(op, opc) \
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
{ \ { \
uint8_t bitmask; \
int sh; \
gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \ gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \ sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
if (sh > 0) \
gen_op_srli_T0(sh); \
else if (sh < 0) \
gen_op_sli_T0(-sh); \
gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \ gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \ sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
if (sh > 0) \
gen_op_srli_T1(sh); \
else if (sh < 0) \
gen_op_sli_T1(-sh); \
gen_op_##op(); \ gen_op_##op(); \
bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
gen_op_andi_T0(bitmask); \
gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \ gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \ gen_op_andi_T1(~bitmask); \
3 - (crbD(ctx->opcode) & 0x03)); \ gen_op_or(); \
gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \ gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
} }
/* crand */ /* crand */