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target/ppc: Fix width of some 32-bit SPRs

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Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit
targets.

This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEXCR,
HDEXCR, CTRL, TSCR, MMCRH, and PMC[1-6] from to be 32-bit registers.

This only goes by the 32/64 classification in the architecture, it
does not try to implement finer details of SPR implementation (e.g.,
not all bits implemented as simple read/write storage).

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-Id: <20230515092655.171206-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-05-15 19:26:47 +10:00 committed by Daniel Henrique Barboza
parent 5260ecffd2
commit fbda88f7ab
6 changed files with 27 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
target/ppc/cpu_init.c
View File

@ -5085,8 +5085,8 @@ static void register_book3s_altivec_sprs(CPUPPCState *env)
}
spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
&spr_read_generic, &spr_write_generic32,
KVM_REG_PPC_VRSAVE, 0x00000000);
}
@ -5120,7 +5120,7 @@ static void register_book3s_207_dbg_sprs(CPUPPCState *env)
spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
KVM_REG_PPC_DAWRX, 0x00000000);
spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
SPR_NOACCESS, SPR_NOACCESS,
@ -5376,7 +5376,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env)
spr_register_hv(env, SPR_TSCR, "TSCR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
0x00000000);
spr_register_hv(env, SPR_HMER, "HMER",
SPR_NOACCESS, SPR_NOACCESS,
@ -5406,7 +5406,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env)
spr_register_hv(env, SPR_MMCRC, "MMCRC",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
0x00000000);
spr_register_hv(env, SPR_MMCRH, "MMCRH",
SPR_NOACCESS, SPR_NOACCESS,
@ -5441,7 +5441,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env)
spr_register_hv(env, SPR_HDSISR, "HDSISR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
0x00000000);
spr_register_hv(env, SPR_HRMOR, "HRMOR",
SPR_NOACCESS, SPR_NOACCESS,
@ -5665,7 +5665,7 @@ static void register_power7_book4_sprs(CPUPPCState *env)
KVM_REG_PPC_ACOP, 0);
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
KVM_REG_PPC_PID, 0);
#endif
}
@ -5730,7 +5730,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env)
{
spr_register(env, SPR_DEXCR, "DEXCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
0);
spr_register(env, SPR_UDEXCR, "DEXCR",
@ -5741,7 +5741,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env)
spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
0);
spr_register(env, SPR_UHDEXCR, "HDEXCR",

2
target/ppc/helper_regs.c
View File

@ -448,7 +448,7 @@ void register_non_embedded_sprs(CPUPPCState *env)
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic32,
KVM_REG_PPC_DSISR, 0x00000000);
spr_register_kvm(env, SPR_DAR, "DAR",
SPR_NOACCESS, SPR_NOACCESS,

4
target/ppc/misc_helper.c
View File

@ -190,13 +190,13 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val)
void helper_store_pidr(CPUPPCState *env, target_ulong val)
{
env->spr[SPR_BOOKS_PID] = val;
env->spr[SPR_BOOKS_PID] = (uint32_t)val;
tlb_flush(env_cpu(env));
}
void helper_store_lpidr(CPUPPCState *env, target_ulong val)
{
env->spr[SPR_LPIDR] = val;
env->spr[SPR_LPIDR] = (uint32_t)val;
/*
* We need to flush the TLB on LPID changes as we only tag HV vs

2
target/ppc/power8-pmu.c
View File

@ -272,7 +272,7 @@ void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value)
{
pmu_update_cycles(env);
env->spr[sprn] = value;
env->spr[sprn] = (uint32_t)value;
pmc_update_overflow_timer(env, sprn);
}

2
target/ppc/spr_common.h
View File

@ -81,6 +81,7 @@ void _spr_register(CPUPPCState *env, int num, const char *name,
void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
@ -109,7 +110,6 @@ void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn);
#ifndef CONFIG_USER_ONLY
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
void spr_write_clear(DisasContext *ctx, int sprn, int gprn);
void spr_access_nop(DisasContext *ctx, int sprn, int gprn);
void spr_read_decr(DisasContext *ctx, int gprn, int sprn);

26
target/ppc/translate.c
View File

@ -411,19 +411,6 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
spr_store_dump_spr(sprn);
}
void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
{
spr_write_generic(ctx, sprn, gprn);
/*
* SPR_CTRL writes must force a new translation block,
* allowing the PMU to calculate the run latch events with
* more accuracy.
*/
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
#if !defined(CONFIG_USER_ONLY)
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
{
#ifdef TARGET_PPC64
@ -436,6 +423,19 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
#endif
}
void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
{
spr_write_generic32(ctx, sprn, gprn);
/*
* SPR_CTRL writes must force a new translation block,
* allowing the PMU to calculate the run latch events with
* more accuracy.
*/
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
#if !defined(CONFIG_USER_ONLY)
void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();